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| anchor | Table_BB_DH |
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| title | Baseboard Design Hints |
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| Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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ED: TODO → Following needs to be updated to new TRM style.
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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| anchor | Table_SIP_B2B |
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| title | General SoC I/O to B2B connectors information |
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Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
| Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| Include Page |
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| PD:4 x 5 SoM LSHM B2B Connectors |
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| PD:4 x 5 SoM LSHM B2B Connectors |
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Technical Specifications
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List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
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Absolute Maximum Ratings *)
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| anchor | Table_TS_AMR |
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| title | Absolute maximum ratings |
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| Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
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*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
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| anchor | Table_TS_ROC |
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| title-alignment | center |
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| title | Recommended operating conditions. |
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JTAG Interface
JTAG access to the TEM0007 SoM through B2B connector JM2.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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JTAG SignalB2B Connector| TMS | JM2-93 | TDI | JM2-95 | TDO | JM2-97 | TCK | JM2-99 | | JTAGSEL | JM1-89 | Pulled Low: Microsemi Polarfire SoC Pulled High: Lattice MachXO CPLD | |
UART Interface
The UART interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
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| anchor | Table_OBP_UART |
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| title | UART interface description |
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SDIO Interface
The SDIO interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
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| anchor | Table_OBP_SDIO |
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| title | SDIO interface description |
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MSSIO Interface
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| Units | Reference Document |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| °C | See ???? datasheet. |
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Physical Dimensions
Module size: ?? mm × ?? mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.
PCB thickness: ?? mm.
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Currently Offered Variants
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Set correct link to the shop page overview table of the product on English and German. Example for TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
| Scroll Title |
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| anchor | Table_OBP_MSSIOVCP_SO |
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| title-alignment | center |
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| title | MSSIO interface descriptionTrenz Electronic Shop Overview |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| FPGA Bank 4 | Connected to | B2B | Notes |
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MSSIO6 - K3 | MIO0 | JM1 - 97 | MSSIO7 - H4 | MIO1 | JM1 - 91 | MSSIO8 - J6 | MIO2 | JM1 - 99 | MSSIO9 - H6 | MIO3 | JM1 - 87 | MSSIO10 - J3 | MIO4 | JM1 - 95 | MSSIO13 - J2 | MIO5 | JM1 - 93 |
SGMII Interface
The Polarfire Soc provides two SGMII interfaces whereby one interface is connected to the B2B connector.
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| anchor | Table_OBP_SGMII |
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| title | SGMII interface description |
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...
MGT Lanes
There are four MGT (Multi Gigabit Transceiver) lanes and two clocks connected between the B2B connector JM3 and the Polarfire SoC bank 5. Each MGT lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, signal schematic name, and board-to-board pin connection:
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| anchor | Table_SIP_MGT |
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| title | MGT Lanes Connection |
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Lane
...
Schematic
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Revision History
Hardware Revision History
| Page properties |
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Set correct links to download Carrier, e.g. TE0706 REV02: TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents Note: - Date format: YYYY-MM-DD
Example: | Date | Revision | Changes | Documentation Link |
|---|
| 2020-11-25 | REV02 | - Resistors R14 and R15 was replaced by 953R (was 5K1)
- Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
| REV02 |
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| Scroll Title |
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| anchor | Figure_RV_HRN |
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| title-alignment | center |
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| title | Board hardware revision number. |
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| draw.io Diagram |
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| border | true |
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| diagramName | Figure_RV_HRN |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | top |
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| lbox | true |
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| diagramWidth | 269 |
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| revision | 1 |
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 Image Added
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| Scroll Title |
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| anchor | Table_RH_HRH |
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| title-alignment | center |
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| title | Hardware Revision History |
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| orientation | portrait |
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| sortDirection | ASC |
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| sortByColumn | 1 |
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| Date | Revision | Changes | Documentation Link |
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| 2020-05-26 | 01 | Inital Release | TEM0007-01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
| Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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| anchor | Table_RH_DCH |
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| title-alignment | center |
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| title | Document change history. |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Contributor | Description |
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| Page info |
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| infoType | Modified date |
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| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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| | Page info |
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| infoType | Modified by |
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| type | Flat |
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| showVersions | false |
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| | -- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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Disclaimer
| Include Page |
|---|
| IN:Legal Notices |
|---|
| IN:Legal Notices |
|---|
|
ED: TODO → Following needs to be updated to new TRM style.
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
...
Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY SGMII interface is connected to the Polarfire SoC.
| Scroll Title |
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| anchor | Table_OBPSIP_ETHB2B |
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| title | Gigabit Ethernet pin descriptionGeneral SoC I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level |
|---|
ETH Pin | Connected to | B2BMDIP[0] - 28 | PHY_MDI0_P | JM1 - 4 | MDIN[0] - 27 | PHY_MDI0_N | JM1 - 6 | MDIP[1] - 24 | PHY_MDI1_P | JM1 - 10 | MDIN[1] - 23 | PHY_MDI1_N | JM1 - 12 | MDIP[2] - 22 | PHY_MDI2_P | JM1 - 16 | MDIN[2] - 21 | PHY_MDI2_N | JM1 - 18 | MDIP[3] - 18 | PHY_MDI3_P | JM1 - 22 | MDIN[3] - 17 | PHY_MDI3_N | JM1 - 24 | |
System Controller CPLD I/O Pins
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
| 0 | JM2 | 18 | 1.2 V / 1.35 V / 1.5 V / 1.8 V | HSIO dependent on VCCIOD | | 0 | JM3 | 16 | 1.2 V / 1.35 V / 1.5 V / 1.8 V | HSIO dependent on VCCIOD | | 1 | JM1 | 48 | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | GPIO dependent on VCCIOB | | 1 | JM2 | 36 | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | GPIO dependent on VCCIOB | | 4 | JM1 | 6 | 3.3 V | MSSIO | | 4 | JM1 | 6 | 3.3 V | SDIO or MSSIO | | 4 | JM1 | 2 | 3.3 V | UART or MSSIO | | 5 | JM3 | 4 | - | SGMII (1 pair for TX / 1 pair for RX) | | 5 | JM3 | 16 | - | SERDES (4 pairs for TX / 4 pairs for RX) | | 5 | JM3 | 4 | - | SERDES CLK (2 pairs for RX) |
|
JTAG Interface
JTAG access to the TEM0007 SoM through B2B connector JM2.
| Page properties |
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
| MIO Pin | Connected to | B2B | Notes |
|---|
| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
| Scroll Title |
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| anchor | Table_OBPSIP_SCJTG |
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| title | System Controller CPLD special purpose pin descriptionJTAG pins connection |
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| orientation | portrait |
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| sortDirection | ASC |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| CPLD Pin | Connected toNotes | TDO - 1 | TDO | JM2 - 97 | TDI - 32TCK 30TMS - 29 | TMS | JM2 - 93 | JTAGENB - 26- 11 | SC_EN1 | JM1 - 28 | - 12 | SC_PGOOD | JM1 - 30 | - 14 | SC_nRST | JM2 - 18 | - 17 | NOSEQ | JM1 - 7 | |
USB Interface
Pulled Low: Microsemi Polarfire SoC Pulled High: Lattice MachXO CPLD |
|
UART Interface
The UART interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionalityUSB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Polarfire SoC. I/O voltage is fixed at 3.3 V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U12).
| Scroll Title |
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| anchor | Table_OBP_USBUART |
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| title | General Overview of the USB PHY SignalsUART interface description |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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PHY Pin| FPGA Bank 4 | Connected to | B2B | Notes |
|---|
DP 18,OTG-D_P | JM3 - 47 | USB data line | | DM - 19 | OTG-D_N | JM3 - 49 | USB data line | | CPEN - 17 | VBUS_EN | JM3 - 53 | External USB power switch | VBUS - 22 | VBUS | JM3 - 55 | ID - 23 | ID | JM3 - 51 | |
Test Points
| H2 | UART_RX | JM1 - 92 |
| | MSSIO12 - H5 | UART_TX | JM1 - 85 |
|
|
SDIO Interface
The SDIO interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
| Scroll Title |
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| anchor | Table_OBP_SDIO |
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| title | SDIO interface description |
|---|
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| Scroll Title |
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| anchor | Table_OBP_TestPoints |
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| title | Test Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Test Point | Signal| FPGA Bank 4 | Connected to | B2B | Notes |
|---|
1 | +3.3V | High-Side Switch, U14 | 2 | +2.5V | Voltage Regulator, U21 | 3 | +2.5V_XCVR | Voltage Regulator, U22 | 4 | +1.8V | Voltage Regulator, U20 | 5 | +1.8V_VDD | High-Side Switch, U13 | 6 | +1.1V_LPDDR4 | Voltage Regulator, U18 | 7 | +1.0V | Voltage Regulator, U19 | 8 | VDDAUX1 | Power Switch, U16 | 9 | AVDD18 | Voltage Regulator, U7 | 10 | AVDD33 | Inductor, L6 | 11 | DVDD1V0 | Voltage Regulator, U7 | 12 | F_TRSTB | FPGA Bank 3 | |
On-board Peripherals
| Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
...
Notes :
...
| MSSIO0 - J1 | SDIO_CLK | JM1 - 27 |
| | MSSIO1 - K5 | SDIO_CMD | JM1 - 25 |
| | MSSIO2 - H1 | SDIO_DAT0 | JM1 - 23 |
| | MSSIO3 - J4 | SDIO_DAT1 | JM1 - 21 |
| | MSSIO4 - K4 | SDIO_DAT2 | JM1 - 19 |
| | MSSIO5 - J7 | SDIO_DAT3 | JM1 - 17 |
|
|
MSSIO Interface
The MSSIO interface is connected from the Polarfire SoC to the B2B connector.
| Scroll Title |
|---|
| anchor | Table_OBP_MSSIO |
|---|
| title | MSSIO interface description |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank 4 | Connected to | B2B | Notes |
|---|
| MSSIO6 - K3 | MIO0 | JM1 - 97 |
| | MSSIO7 - H4 | MIO1 | JM1 - 91 |
| | MSSIO8 - J6 | MIO2 | JM1 - 99 |
| | MSSIO9 - H6 | MIO3 | JM1 - 87 |
| | MSSIO10 - J3 | MIO4 | JM1 - 95 |
| | MSSIO13 - J2 | MIO5 | JM1 - 93 |
|
|
SGMII Interface
The Polarfire Soc provides two SGMII interfaces whereby one interface is connected to the B2B connector.
| Scroll Title |
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| anchor | Table_OBP_SGMII |
|---|
| title | On board peripheralsSGMII interface description |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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System Controller CPLD
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
Gigabit Ethernet
| U2 - N8 | SGMII1_OUT_N | JM3 - 1 |
| | U2 - M7 | SGMII1_OUT_P | JM3 - 3 |
| | U2 - K7 | SGMII1_IN_N | JM2 - 2 |
| | U2 - K6 | SGMII1_IN_P | JM2 - 4 |
|
|
MGT Lanes
There are four MGT (Multi Gigabit Transceiver) lanes and two clocks connected between the B2B connector JM3 and the Polarfire SoC bank 5. Each MGT lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, signal schematic name, and board-to-board pin connection:On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U8).
| Scroll Title |
|---|
| anchor | Table_OBPSIP_ETHMGT |
|---|
| title | Ethernet PHY to Polarfire SoC connectionsMGT Lanes Connection |
|---|
|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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SoC U2Signal NameETH| Signal Description | Bank 5 - N6 | SGMII0_INU7 1SGMII Data Positive | Bank 5 - N7 |
| | 0 | XCVR_RX0_N | JM3-28 |
| | 0 | XCVR_TX0 |
SGMII0_INU7 2SGMII Data Negativ | Bank 5 - L5 | | 25 |
| | 0 | XCVR_TX0_P | JM3-27 |
| | 1 | XCVR_RX1 |
SGMII0_OUTU7 4SGMII Data Positive | Bank 5 - L6 | SGMII0_OUTU7 5SGMII Data Negativ | Bank 2 - D3 | ETH_MDC | U7 - 7 | Management Data Clock | Bank 2 - C2 | ETH_MDIO | U7 - 8 | Management Date I/O | Bank 2 - E5 | ETH_RST | U7 - 16 | Hardware Reset | | Bank 1 - AA16 | PHY_LED0 | U7 - 14 | LED Output | via voltage-level translator | | Bank 1 - Y16 | PHY_LED1 | U7 - 13 | LED Output | via voltage-level translator | | Bank 1 - Y14 | PHY_LED2 | U7 - 12 | LED Output | via voltage-level translator | |
USB PHY
| 22 |
| | 1 | XCVR_TX1_P | JM3-19 |
| | 1 | XCVR_TX1_N | JM3-21 |
| | 2 | XCVR_RX2_P | JM3-14 |
| | 2 | XCVR_RX2_N | JM3-16 |
| | 2 | XCVR_TX2_P | JM3-13 |
| | 2 | XCVR_TX2_N | JM3-15 |
| | 3 | XCVR_RX3_P | JM3-8 |
| | 3 | XCVR_RX3_N | JM3-10 |
| | 3 | XCVR_TX3_P | JM3-7 |
| | 3 | XCVR_TX3_N | JM3-9 |
| | CLK | XCVR_CLK0_P | JM3-33 |
| | CLK | XCVR_CLK0_P | JM3-31 |
| | CLK | XCVR_CLK1_P | JM3-32 |
| | CLK | XCVR_CLK1_N | JM3-34 |
|
|
Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY SGMII Hi-speed USB ULPI PHY (U11) is provided with USB3320 from Microchip. The ULPI interface is connected to the Polarfire SoC via MSSIO14...25 bank 2. The I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U12)..
| scroll-scroll-title |
|---|
| anchor | Table_OBP_USBETH |
|---|
| title | USB PHY to Polarfire SoC connectionsGigabit Ethernet pin description |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
| Bank 2 | Signal Name | USB | Signal Description |
|---|
U2 - G4 | OTG-STP | U11 - 29 | Stop |
| U2 - G5 | OTG-NXT | U11 - 2 | Next |
U2 - F1 | OTG-DIR | U11 - 31 | Direction |
| U2 - G2 | OTG-CLK | U11 - 1 | Clock |
| U2 - F2 | OTG_DATA0 | U11 - 3 | ULPI bi-directional data bus |
| U2 -E1 | OTG_DATA1 | U11 - 4 | ULPI bi-directional data bus |
| U2 -G3 | OTG_DATA2 | U11 - 5 | ULPI bi-directional data bus |
| U2 -F5 | OTG_DATA3 | U11 - 6 | ULPI bi-directional data bus |
| U2 - D1 | OTG_DATA4 | U11 - 7 | ULPI bi-directional data bus |
| U2 -D2 | OTG_DATA5 | U11 - 9 | ULPI bi-directional data bus |
| U2 -F6 | OTG_DATA6 | U11 - 10 | ULPI bi-directional data bus |
| U2 - F3 | OTG_DATA7 | U11 - 13 | ULPI bi-directional data bus |
| U2 - E4 | OTG-RST | U11 - 27 | Reset |
LPDDR4 SDRAM
| Page properties |
|---|
|
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEM0007 SoM has a one GByte volatile LPDDR4 SDRAM IC for storing user application code and data.
- Part number: IS43LQ32256A-062BLI
- Supply voltage: +1.8 V / +1.1 V
- Speed: 1600 MHz
- Temperature: Industrial (-40°C to +85°C)
EEPROM
There is a 2 Kbit EEPROM provided on the module TEM0007 with a pre-programmed globally unique MAC.
...
| anchor | Table_OBP_EEP |
|---|
| title | I2C EEPROM interface MSSIOs and pins |
|---|
| ETH Pin | Connected to | B2B | Notes |
|---|
| MDIP[0] - 28 | PHY_MDI0_P | JM1 - 4 |
| | MDIN[0] - 27 | PHY_MDI0_N | JM1 - 6 |
| | MDIP[1] - 24 | PHY_MDI1_P | JM1 - 10 |
| | MDIN[1] - 23 | PHY_MDI1_N | JM1 - 12 |
| | MDIP[2] - 22 | PHY_MDI2_P | JM1 - 16 |
| | MDIN[2] - 21 | PHY_MDI2_N | JM1 - 18 |
| | MDIP[3] - 18 | PHY_MDI3_P | JM1 - 22 |
| | MDIN[3] - 17 | PHY_MDI3_N | JM1 - 24 |
|
|
System Controller CPLD I/O Pins
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
| Page properties |
|---|
|
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
|---|
| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
|
| Scroll Title |
|---|
| anchor | Table_OBP_SC |
|---|
| title | System Controller CPLD special purpose pin description |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| CPLD Pin | Connected to | B2B | Notes |
|---|
| TDO - 1 | TDO | JM2 - 97 |
| | TDI - 32 | TDI | JM2 - 95 |
| | TCK - 30 | TCK | JM2 - 99 |
| | TMS - 29 | TMS | JM2 - 93 |
| | JTAGENB - 26 | JTAGSEL | JM1 - 89 |
| - 11 | SC_EN1 | JM1 - 28 |
| | - 12 | SC_PGOOD | JM1 - 30 |
| | - 14 | SC_nRST | JM2 - 18 |
| | - 17 | NOSEQ | JM1 - 7 |
|
|
USB Interface
USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Polarfire SoC. I/O voltage is fixed at 3.3 V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U12).
...
| Scroll Title |
|---|
| anchor | Table_OBP_I2C_EEPROMUSB |
|---|
| title | I2C address for EEPROMGeneral Overview of the USB PHY Signals |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
MSSIO I2C AddressDesignator| MSSIO26...27 | 0x50 | U10 | |
SPI Flash Memory
| Page properties |
|---|
|
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
...
DP - 18, | OTG-D_P | JM3 - 47 | USB data line | | DM - 19 | OTG-D_N | JM3 - 49 | USB data line | | CPEN - 17 | VBUS_EN | JM3 - 53 | External USB power switch | | VBUS - 22 | VBUS | JM3 - 55 |
| | ID - 23 | ID | JM3 - 51 |
|
|
Test Points
| Scroll Title |
|---|
| anchor | Table_OBP_SPITestPoints |
|---|
| title | SPI Flash interface pinsTest Points Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
| Polarfire SoC Pin | Schematic | U3 Pin | Notes |
|---|
SCK_3 - E6 | SPI_SCK | CLK - B2 | SS_3 - G7 | SPI_SS | CS# - C2 | SDO_3 - F7 | SPI_SDO | DI/IO0 - D3 | SDI_3 - H10 | SPI_SDI | DO/IO1 - D2 | SPI_EN_3 - H11 | SPI_EN | - |
Oscillators
...
| anchor | Table_OBP_CLK |
|---|
| title | Osillators |
|---|
| Test Point | Signal | Connected to | Notes |
|---|
| 1 | +3.3V | High-Side Switch, U14 |
| | 2 | +2.5V | Voltage Regulator, U21 |
| | 3 | +2.5V_XCVR | Voltage Regulator, U22 |
| | 4 | +1.8V | Voltage Regulator, U20 |
| | 5 | +1.8V_VDD | High-Side Switch, U13 |
| | 6 | +1.1V_LPDDR4 | Voltage Regulator, U18 |
| | 7 | +1.0V | Voltage Regulator, U19 |
| | 8 | VDDAUX1 | Power Switch, U16 |
| | 9 | AVDD18 | Voltage Regulator, U7 |
| | 10 | AVDD33 | Inductor, L6 |
| | 11 | DVDD1V0 | Voltage Regulator, U7 |
| | 12 | F_TRSTB | FPGA Bank 3 |
|
|
On-board Peripherals
...
| Page properties |
|---|
| In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
| Page properties |
|---|
|
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| Scroll Title |
|---|
| anchor | Table_PWR_PCOBP |
|---|
| title | Power ConsumptionOn board peripherals |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
| Power Input Pin | Typical Current |
|---|
| VIN | TBD* |
| 3.3VIN | TBD* |
* TBD - To Be Determined
Power Distribution Dependencies
...
| anchor | Figure_PWR_PD |
|---|
| title | Power Distribution |
|---|
...
System Controller CPLD
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U8)
...
| Scroll Only |
|---|
 Image Removed
|
Power-On Sequence
The power sequence is the recommended one. The final sequence depends on the system controller.
| Scroll Title |
|---|
| anchor | FigureTable_PWROBP_PSETH |
|---|
| title | Power SequencyEthernet PHY to Polarfire SoC connections |
|---|
|
| ignoredrawiobordertrue |
| diagramName | TEM0007_PWR_PS |
|---|
| simpleViewer | false |
|---|
width | | links | auto |
|---|
| tbstyle | top |
|---|
| lbox | true |
|---|
| diagramWidth | 531 |
|---|
| revision | 5 |
|---|
| Scroll Only |
|---|
 Image Removed
|
Voltage Monitor Circuit
The TEM0007 delivers two voltage monitor circuits. The first circuit is responsible for the selection of voltage "VDDAUX1". This voltage is selected on the basis of the voltage of "VCCIOB". If "VCCIOB" is higher than 2.9 V, "VDDAUX1" should be +3.3 V. If it is smaller, "VDDAX1" should be +2.5 V. The second circuit monitors the +1.0 V power rail. According to this rail, the reset is set/unset to realize a brown-out detection. Furthermore, a possibility for a manual reset is available.
...
| anchor | Figure_PWR_VMC |
|---|
| title | Voltage Monitor Circuit |
|---|
...
| ASC | | repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| SoC U2 | Signal Name | ETH | Signal Description |
|
|---|
Bank 5 - N6 | SGMII0_IN_P | U7 - 1 | SGMII Data Positive |
| | Bank 5 - N7 | SGMII0_IN_N | U7 - 2 | SGMII Data Negativ |
| Bank 5 - L5 | SGMII0_OUT_P | U7 - 4 | SGMII Data Positive |
| | Bank 5 - L6 | SGMII0_OUT_N | U7 - 5 | SGMII Data Negativ |
| | Bank 2 - D3 | ETH_MDC | U7 - 7 | Management Data Clock |
| | Bank 2 - C2 | ETH_MDIO | U7 - 8 | Management Date I/O |
| | Bank 2 - E5 | ETH_RST | U7 - 16 | Hardware Reset |
| | Bank 1 - AA16 | PHY_LED0 | U7 - 14 | LED Output | via voltage-level translator | | Bank 1 - Y16 | PHY_LED1 | U7 - 13 | LED Output | via voltage-level translator | | Bank 1 - Y14 | PHY_LED2 | U7 - 12 | LED Output | via voltage-level translator |
|
USB PHY
Hi-speed USB ULPI PHY (U11) is provided with USB3320 from Microchip. The ULPI interface is connected to the Polarfire SoC via MSSIO14...25 bank 2. The I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U12).
| Scroll Title |
|---|
| anchor | Table_OBP_USB |
|---|
| title | USB PHY to Polarfire SoC connections |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Bank 2 | Signal Name | USB | Signal Description |
|---|
U2 - G4 | OTG-STP | U11 - 29 | Stop | | U2 - G5 | OTG-NXT | U11 - 2 | Next | U2 - F1 | OTG-DIR | U11 - 31 | Direction | | U2 - G2 | OTG-CLK | U11 - 1 | Clock | | U2 - F2 | OTG_DATA0 | U11 - 3 | ULPI bi-directional data bus | | U2 -E1 | OTG_DATA1 | U11 - 4 | ULPI bi-directional data bus | | U2 -G3 | OTG_DATA2 | U11 - 5 | ULPI bi-directional data bus | | U2 -F5 | OTG_DATA3 | U11 - 6 | ULPI bi-directional data bus | | U2 - D1 | OTG_DATA4 | U11 - 7 | ULPI bi-directional data bus | | U2 -D2 | OTG_DATA5 | U11 - 9 | ULPI bi-directional data bus | | U2 -F6 | OTG_DATA6 | U11 - 10 | ULPI bi-directional data bus | | U2 - F3 | OTG_DATA7 | U11 - 13 | ULPI bi-directional data bus | | U2 - E4 | OTG-RST | U11 - 27 | Reset |
|
LPDDR4 SDRAM
| Page properties |
|---|
|
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEM0007 SoM has a one GByte volatile LPDDR4 SDRAM IC for storing user application code and data.
- Part number: IS43LQ32256A-062BLI
- Supply voltage: +1.8 V / +1.1 V
- Speed: 1600 MHz
- Temperature: Industrial (-40°C to +85°C)
EEPROM
There is a 2 Kbit EEPROM provided on the module TEM0007 with a pre-programmed globally unique MAC.
| Scroll Title |
|---|
| anchor | Table_OBP_EEP |
|---|
| title | I2C EEPROM interface MSSIOs and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| MSSIO Pin | Schematic | U10 Pin | Notes |
|---|
| 26 | I2C_SCL | SCL - 1 |
| | 27 | I2C_SDA | SDA - 3 |
|
|
| Scroll Title |
|---|
| anchor | Table_OBP_I2C_EEPROM |
|---|
| title | I2C address for EEPROM |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| MSSIO Pin | I2C Address | Designator | Notes |
|---|
| MSSIO26...27 | 0x50 | U10 |
|
|
SPI Flash Memory
| Page properties |
|---|
|
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TEM0007 is equipped with a MT25QU512ABB8E12-0SIT flash memory chip, U3, which provided storage for FPGA configuration files. After configuration, the remaining free memory can be used for application data storage.
...
| Scroll Only |
|---|
 Image Removed
|
Power Rails
| Scroll Title |
|---|
| anchor | Table_PWROBP_PRSPI |
|---|
| title | Module power rails.SPI Flash interface pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Power Rail Name | B2B Connector JM1 B2B Connector JM2 Pin | Direction | Notes | | VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board | | 3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board | | 3.3VIN | - | 91 | Output | JTAG reference voltage | | +1.8V | 39 | - | Output | Internal +1.8V voltage level | VCCIOB | - | 1, 3 | Input | General purpose I/O bank voltage | | VCCIOD | - | 7, 9 | Input | High speed I/O bank voltage (max. +1.8 V) | | +3.3V | - | 10, 12 | Output | Internal +3.3 V voltage level | |
...
| Schematic | U3 Pin | Notes |
|---|
| SCK_3 - E6 | SPI_SCK | CLK - B2 |
| | SS_3 - G7 | SPI_SS | CS# - C2 |
| | SDO_3 - F7 | SPI_SDO | DI/IO0 - D3 |
| | SDI_3 - H10 | SPI_SDI | DO/IO1 - D2 |
| | SPI_EN_3 - H11 | SPI_EN | - |
|
|
Oscillators
| Scroll Title |
|---|
| anchor | Table_PWROBP_BVCLK |
|---|
| title | Polarfire SoC bank voltages.Osillators |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | widths |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic Name | | Notes |
|---|
|
| Bank 0 HSIO | VCCIOD | Variable | max. voltage +1.8 V |
| Bank 1 GPIO | VCCIOB | Variable | max. voltage +3.3 V |
Bank 2 MSSIO | +3.3V | +3.3 V | Bank 3 | +1.8V | +1.8 V | Bank 4 MSSIO | +3.3V | +3.3 V | Bank 5 | +3.3V | +3.3 V | Bank 6 MSS DDR | +1.1V_LPDDR4 | +1.1 V |
...
...
use "include page" macro and link to the general B2B connector page of the module series,
| |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Description | Frequency | Note |
|---|
| U4 | MSS REFCLK | 125 MHz |
| | U5 | SERDES CLK | 125 MHz |
| | U12 | USB | 52 MHz |
|
|
Power and Power-On Sequence
| Page properties |
|---|
|
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
|
Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
...
Technical Specifications
...
| Scroll Title |
|---|
| anchor | Table_TSPWR_AMRPC |
|---|
| title | Absolute maximum ratingsPower Consumption |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
| Symbols | Description | Min | Max | Unit |
|---|
| VIN | Supply voltage | -0.3 | 6.0 | V |
| 3.3VIN | Supply voltage | -0.3 | 3.6 | V |
VCCIOB | I/O bank voltage | -0.5 | 3.6 | V |
| VCCIOD | I/O bank voltage | -0.5 | 2.0 | V |
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
...
| anchor | Table_TS_ROC |
|---|
| title | Recommended operating conditions. |
|---|
...
VCCIOB
...
Physical Dimensions
Module size: 40 mm × 50 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.74 mm.
...
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.
For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
| Note |
|---|
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
...
| anchor | Figure_TS_PD |
|---|
| title | Physical Dimension |
|---|
...
| Scroll Only |
|---|
| scroll-pdf | true |
|---|
| scroll-office | true |
|---|
| scroll-chm | true |
|---|
| scroll-docbook | true |
|---|
| scroll-eclipsehelp | true |
|---|
| scroll-epub | true |
|---|
| scroll-html | true |
|---|
|
 Image Removed
|
Currently Offered Variants
| Page properties |
|---|
|
Set correct link to the shop page overview table of the product on English and German. Example for TE0728: ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
...
| anchor | Table_VCP_SO |
|---|
| title | Trenz Electronic Shop Overview |
|---|
...
Revision History
Hardware Revision History
...
Set correct links to download arrier, e.g. TE0706 REV02:
TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents
Note:
| Power Input Pin | Typical Current |
|---|
| VIN | TBD* | | 3.3VIN | TBD* |
|
* TBD - To Be Determined
Power Distribution Dependencies
| Scroll Title |
|---|
| anchor | Figure_PWR_PD |
|---|
| title | Power Distribution |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| |
|---|
| diagramName | TEM0007_PWR_PD |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | top |
|---|
| lbox | true |
|---|
| diagramWidth | 512 |
|---|
| revision | 2 |
|---|
|
|
| Scroll Only |
|---|
Image Added |
|
Power-On Sequence
The power sequence is the recommended one. The final sequence depends on the system controller.
| Scroll Title |
|---|
| anchor | Figure_PWR_PS |
|---|
| title | Power Sequency |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| |
|---|
| diagramName | TEM0007_PWR_PS |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | top |
|---|
| lbox | true |
|---|
| diagramWidth | 531 |
|---|
| revision | 5 |
|---|
|
|
| Scroll Only |
|---|
Image Added |
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Voltage Monitor Circuit
The TEM0007 delivers two voltage monitor circuits. The first circuit is responsible for the selection of voltage "VDDAUX1". This voltage is selected on the basis of the voltage of "VCCIOB". If "VCCIOB" is higher than 2.9 V, "VDDAUX1" should be +3.3 V. If it is smaller, "VDDAX1" should be +2.5 V. The second circuit monitors the +1.0 V power rail. According to this rail, the reset is set/unset to realize a brown-out detection. Furthermore, a possibility for a manual reset is available.
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| anchor | Figure_PWR_VMC |
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| title | Voltage Monitor Circuit |
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| diagramName | TEM0007_PWR_VM |
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Power Rails
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | Direction | Notes |
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| VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board | | 3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board | | 3.3VIN | - | 91 | Output | JTAG reference voltage | | +1.8V | 39 | - | Output | Internal +1.8V voltage level | VCCIOB | - | 1, 3 | Input | General purpose I/O bank voltage | | VCCIOD | - | 7, 9 | Input | High speed I/O bank voltage (max. +1.8 V) | | +3.3V | - | 10, 12 | Output | Internal +3.3 V voltage level |
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Bank Voltages
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| anchor | Table_PWR_BV |
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| title | Polarfire SoC bank voltages. |
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| Schematic Name | | Notes |
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| Bank 0 HSIO | VCCIOD | Variable | max. voltage +1.8 V | | Bank 1 GPIO | VCCIOB | Variable | max. voltage +3.3 V | | Bank 2 MSSIO | +3.3V | +3.3 V |
| | Bank 3 | +1.8V | +1.8 V |
| | Bank 4 MSSIO | +3.3V | +3.3 V |
| | Bank 5 | +3.3V | +3.3 V |
| | Bank 6 MSS DDR | +1.1V_LPDDR4 | +1.1 V |
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Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| Include Page |
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| PD:4 x 5 SoM LSHM B2B Connectors |
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| PD:4 x 5 SoM LSHM B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
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| anchor | Table_RHTS_HRHAMR |
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| title | Hardware Revision HistoryAbsolute maximum ratings |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| cellHighlighting | true |
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| Date | Revision | Changes | Documentation Link |
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| 2020-05-26 | 01 | Inital Release | REV01 |
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| Symbols | Description | Min | Max | Unit |
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| VIN | Supply voltage | -0.3 | 6.0 | V |
| 3.3VIN | Supply voltage | -0.3 | 3.6 | V |
VCCIOB | I/O bank voltage | -0.5 | 3.6 | V |
| VCCIOD | I/O bank voltage | -0.5 | 2.0 | V |
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for optionsHardware revision number can be found on the PCB board together with the module model number separated by the dash.
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| anchor | FigureTable_RVTS_HRNROC |
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| title | Board hardware revision numberRecommended operating conditions. |
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ignore| draw.io Diagram |
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| diagramName | TEM0007_RV_HRN |
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width | | links | auto |
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| tbstyle | top |
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| lbox | true |
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| diagramWidth | 494 |
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| revision | 3 |
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Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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| anchor | Table_RH_DCH |
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| title | Document change history. |
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| sortByColumn | 1 |
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| Parameter | Min | Max | Units | Reference Document |
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| VIN | 2.7 | 5.5 | V | See EN6363Q, EP53A7LQI, and EP53A7HQI datasheets. | | 3.3VIN | 3.14 | 3.46 | V | See 88E1512 datasheet. | VCCIOB | 1.14 | 3.465 | V | See MPFS250T datasheet. | | VCCIOD | 1.14 | 1.89 | V | See MPFS250T datasheet. |
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Physical Dimensions
Module size: 40 mm × 50 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.74 mm.
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| infoType | Current version |
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Disclaimer
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