Page History
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(ED: Tabelle ist fertig!)
Changes
#1
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Type:
Reason:
Impact:
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Changed DCDC EN63A0QI (U14) to MP8869SGL-Z and adapted power circuit.
Type: Schematic Change
Reason: EOL of Component.
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Reason: Keep FPGA in reset while signal "PROG_B" is low during initial power-up.
Impact: None.
#11 Connect U14 to I2C bus via resistors (R91, R92) and pull-up resistors (R45, R47).
Type: Schematic Change
Reason: Improvement of DCDC handling.
Impact: None. I2C bus has additional device.
#5 Added pull-up resistor (R71) for signal "SPI_DQ2".
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Impact: Changed trace length have to be taken into account in existing designs. The trace length for new revision will be available in TE0713 series pinout generator. Please check if change in trace length still matches your requirements. Adaption of carrier may be necessary.
#5 Added common mode voltage setting via resistors (R62, R64, R65,
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R66) for clock signals "PLL_CLK_P" and "PLL_CLK_N" termination.
Type: Schematic Change
Reason: Improve clock termination.
Impact: None.
#9 Added capacitor (C184) for FPGA.
Type: Schematic Change
Reason: Follow AMD recommendation.
Impact: None.
#9 Changed capacitor (C80, C177) from 47 µF, 6.3 V 0805 to 22 µF, 10 V, 0603.
Type: Schematic Change
Reason: BOM Optimization.
Impact: None.
#9 Changed capacitor (C2, C4, C5, C53, C158) from 0805 to 0603.
Type: Schematic Change
Reason: BOM Optimization.
Impact: None.
#9 Changed 100 µF capacitors (C35, C45, C120, C144, C145, C146, C147, C148, C149) from 6.3 V, X5R, 1206 to 4 V, X6S, 0805.
Type: Schematic Change
Reason: BOM Optimization.
Impact: None.
#9 Changed capacitor (C103, C104) from 50 V 0402 to 25 V, 0201.
Type: Schematic Change
Reason: BOM Optimization.
Impact: None.
#5 Connected signal "RD_N" to FPGA via level translator (U10).
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Reason: Signal termination.
Impact: None.
#5 Changed resistors (R2, R7, R8, R29, R67, R68) from 4.87 kOhm to 4.7 kOhm.
Type: Schematic Change
Reason: BOM optimization.
Impact: None.
#5 Changed resistors (R53, R54) from 1 kOhm to 1.6 kOhm.
Type: Schematic Change
Reason: BOM optimization.
Impact: None.
#5 Changed resistor (R3) from 0402 63 mW to 0201 50 mW.
Type: Schematic Change
Reason: BOM optimization.
Impact: None.
#5 Removed testpoints from bottom PCB side for signals "3.3VIN", "RESIN", "JTAGEN", "TMS", "TCK", "TDI", and "TDO".
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Reason: Optimize placement.
Impact: None.
#5 Added testpoints (
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TP23, TP24, TP25, TP26, TP27, TP28, TP29, TP30, TP31, TP32, TP33, TP34, TP39, TP40, TP(???
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for AVCC).
Type: Schematic Change
Reason: Optimize placement.Optimized placement.
Impact: None.
#17 Updated components from library.
Type: Schematic Change
Reason: Use latest component data.
Impact: None.
#20 Added legal notices, system and power overview. Updated revision Updated revision history. Updated page count and order.
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