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Table of Contents

Table of Contents

Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/TE0710+TRM for online version of this manual and the rest of available documentation.

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Trenz Electronic TE0710 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, two 10/100 Mbit Ethernet PHYs, 512 MByte DDR3 SDRAM, 32 MByte Quad SPI Flash memory for configuration and operation and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

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Voltages on B2B-

Connectors

B2B JM1-PinB2B JM2-PinDirectionNote
VIN

1, 3, 5

2, 4, 6, 8InputSupply voltage
3.3VIN13, 15-InputSupply voltage
VCCIO159, 11-InputHigh range bank voltage
VCCIO34-7, 9InputHigh range bank voltage
3.3V14-10, 12, 91OutputInternal 3.3V voltage level
JTAG VREF-91OutputJTAG reference voltage (3.3V).
1.8V39-OutputInternal 1.8V voltage level
1.5V-19OutputInternal 1.5V voltage level

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Board to Board Connectors

Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B ConnectorsIN:Samtec LSHMIN:Samtec LSHM

Variants Currently In Production

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  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.
  • Mating height with standard connectors: 8mm
  • PCB thickness: 1.6mm4mm+/-10%
  • Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.

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Figure 3: Physical dimensions of the TE0710-02 SoM.

Weight

11.5 g - Plain module.

8.8 g - Set of nuts and bolts.

Revision History

Hardware Revision History

Revision History

Hardware Revision History

DateRevisionNotesPCNDocumentation Link
2014-03-0702Current hardware version 
TE0710-02

 01First production release  

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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DateRevisionContributorsDescription
2017

page-

01

Info
modified-

26

date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
prefixv.
typeFlat

Page info
infoTypeModified by
typeFlat

  • correction pcb thickness
  • change history style
2018-04-20v.9John Hartfiel
  • Update power rail section
2017-11-10v.5John Hartfiel
  • Replace B2B connector section
2017-01-26v.4Jan Kumann
  • New block diagram.
2017-01-24

v.3

Jan Kumann

New block diagram.

2017-01-24

V3

Jan Kumann
  • SC I/O pins section improved.
2017-01-01
V2v.2

Jan Kumann

  • TRM revision.
2015-01-23V1v.1

Page info
infoTypeModified users
typeFlat

Antti Lukats, Emmanuel Vassilakis, Ali Naseri

  • Initial version.

Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices