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Template Revision 2.8 - on construction
Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Important General Note:
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Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table of contents
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Overview
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Zynq PS Design with DDR Less FSBL Example.
Refer to http://trenz.org/te0722-info for the current online version of this manual and other available documentation.
Key Features
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- 2019.2 update
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- split FSBL into 2 templates, one with and one without Sensor+LED access example app
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- TE Script update
- rework of the FSBLs
- DDR LESS, Device ID, Sensor+LED access
- VIO for RGB access
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- initial release
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Overview
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Zynq PS Design with DDR Less FSBL Example.
Refer to http://trenz.org/te0722-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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- Option1:
- In case Flash is empty, use fsbl_flash on programming GUI
- In case Flash is programmed use normal fsbl on programming GUI
- Option2: use in both case fsbl_flash on programming GUI and Vivado LabTools 2018.3
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Release Notes and Know Issues
Requirements
Software
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title | Software |
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- list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
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Design supports following carriers:
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Additional HW Requirements:
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Additional HW Requirements:
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for JTAG, UART
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Content
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For general structure and of the reference design, see Project Delivery - Xilinx devices
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For general structure and of the reference design, see Project Delivery - AMD devices
Design Sources
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Additional Sources
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Additional Sources
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Debian SD-Image
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*.img
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Debian Image for SD-Card
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Prebuilt
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MCS-File
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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Converted Software Application for MicroBlaze Processor Systems
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anchor | Table_PF |
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title | Prebuilt files (only on ZIP with prebult content) |
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File
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File-Extension
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Description
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
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The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/
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Vitis GUI.
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For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
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- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create
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- project and follow
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- instructions of the product selection guide
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- , settings file will be configured automatically during this process.
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optional for manual changes
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: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see
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also Vivado Board Part
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Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
TE::hw_build_design -export_prebuilt
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Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Generate Programming Files with
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- Vitis
Run on Vivado TCL:
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
(alternative) Start
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Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Projects contains 3 FSBL template: zynq_fsbl (FSBL modified for DDR Less application → use for Boot.bin), zynq_fsbl_app (FSBL modified for DDR Less application and with demo app included → create Boot with this FSBL and Bitstream only), zynq_fsbl_flash(FSBL modified for Flash programming →FSBL which must be selected separately to program Flash)Info TE0722 is without DDR, so special FSBL (sources on reference designs) is needed, see also: DDR less ZYNQ Design
Launch
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Basic Information, see TE0722 Getting Started
Programming
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Check Module and Carrier TRMs for proper HW configuration |
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before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/
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Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select
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create and open delivery binary folder
Info Note: Folder
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"<project
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<Article Name>
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" with subfolder
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"boot_<app name>
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" for different applications will be generated
QSPI-Boot mode
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Option for Boot.bin on QSPI Flash
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console:
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Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp zynq_fsbl_app
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TE::pr_program_flash -swapp hello_te0820 (optional)
SD-Boot mode
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Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot only. See also Xilinx AR#66846
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section
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- Programming
- Connect UART USB (most cases same as JTAG)
Power On PCB
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Expand title boot process 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL
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init PS, programs PL using the bitstream
3. FSBL starts application (included into the FSBL Code)
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Standalone Application
Note: UART over J2 is used, this is only available, if PL part is configured with correct UART connection.
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
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Info Win OS, see device manager, Linux OS
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see dmesg |grep
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tty (UART is *USB1)
- Output:
- Default output appears only 10
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- times. Reboot device: force ResN Pin to GND for short time, location see: TE0722 Getting Started
- times. Reboot device: force ResN Pin to GND for short time, location see: TE0722 Getting Started
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- Image Added
- Image Added
Vivado HW Manager
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- Enable/Disable RGB LED Counter (default on)
- Enable/Disable different colors (default all off)
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System Design - Vivado
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PS Interfaces
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Basic module
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constraints
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# Common BITGEN related settings for TE0722
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific
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set_property PACKAGE_PIN K15 [get_ports UART_0_txd]
set_property PACKAGE_PIN L13 [get_ports UART_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_0_*] |
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#RGB LED
#R
set_property PACKAGE_PIN J15 [get_ports {RGB_LED[0]}]
#G
set_property PACKAGE_PIN L14 [get_ports {RGB_LED[1]}]
#B
set_property PACKAGE_PIN K12 [get_ports {RGB_LED[2]}]
set_property IOSTANDARD LVCMOS33 |
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Software Design - Vitis
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Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf |
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is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Source location: \sw_lib\sw_apps
zynq_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
- Disable Memory initialisation on main.c
zynq_fsbl_app
Source location: \sw_lib\sw_apps
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TE modified 2019.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod'
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Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
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- Display FSBL Banner and Device ID
- Disable Memory initialisation on main.c
- on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
- Disable Memory initialisation on main.c
Module Specific:
- Add Files: all TE Files start with te_*
- Example app for LED access over MIO and sensor access over I2C
- SD Card access read/write file
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation on main.c
Additional Software
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No additional software is needed.
zynq_fsbl_app
TE modified 2019.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
- Disable Memory initialisation on main.c
Module Specific:
- Add Files: all TE Files start with te_*
- Example app for LED access over MIO and sensor access over I2C
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
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Appx. A: Change History and Legal Notices
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Document Change History
To get content of older
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