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This SoM has following peripherals on board:
- 1 x Gbps Ethernet Phy PHY transceiver
- 2 x 100 Mbps Ethernet PHY transceivers
- 512 MByte DDR3 Memory
- 32 MByte SPI Flash Memory
- eMMC (4GByte 4 GByte in standard configuration)
- USB PHY transceiver
- powerful switch-mode power supplies for all on-board voltages
- large number of configurable I/Os is provided via rugged high-speed stacking strips
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Default MIO mapping:
| MIO | Configured as | B2B | Notes |
|---|---|---|---|
| 00 | GPIO | J2-87 | B2B |
| 1 | QSPI0 | - | SPI Flash-CS |
| 2 | QSPI0 | - | SPI Flash-DQ0 |
| 3 | QSPI0 | - | SPI Flash-DQ1 |
| 4 | QSPI0 | - | SPI Flash-DQ2 |
| 5 | QSPI0 | - | SPI Flash-DQ3 |
| 6 | QSPI0 | - | SPI Flash-SCK |
| 7 | GPIO | - | Red LED D8 |
| 8 | - | - | - |
| 9 | GPIO | J2-88 | B2B |
| 10 | I2C0 SDA | J2-90 | B2B |
| 11 | I2C0 SCL | J2-92 | B2B |
| 12 | I2C1 SDA | J2-93 | B2B (SDA on-board I2C, also configurable as GPIO by user) |
| 13 | I2C1 SCL | J2-95 | B2B (SCL on-board I2C, also configurable as GPIO by user) |
| 14 | USART0 RX | J2-94 | B2B (RX on-board UART, also configurable as GPIO by user) |
| 15 | USART0 TX | J2-96 | B2B (TX on-board UART, also configurable as GPIO by user) |
| 16..27 | ETH0 | RGMII | |
| 28..39 | USB0 | ULPI | |
| 40 | SDIO0 | J2-100 | B2B depending on state of pin MIO48 'SEL_SD' |
| 41 | SDIO0 | J2-102 | B2B depending on state of pin MIO48 'SEL_SD' |
| 42 | SDIO0 | J2-104 | B2B depending on state of pin MIO48 'SEL_SD' |
| 43 | SDIO0 | J2-106 | B2B depending on state of pin MIO48 'SEL_SD' |
| 44 | SDIO0 | J2-108 | B2B depending on state of pin MIO48 'SEL_SD' |
| 45 | SDIO0 | J2-110 | B2B depending on state of pin MIO48 'SEL_SD' |
| 46 | GPIO | - | RTC Interrupt |
| 47 | - | - | - |
| 48 | GPIO | SEL_SD | select source between e-MMC / baseboard SD-Card |
| 49 | GPIO | - | USB Reset |
| 50 | GPIO | - | ETH0 Interrupt |
| 51 | GPIO | - | ETH0 Reset |
| 52 | ETH0 | - | MDC |
53 | ETH0 | - | MDIO |
I2C Interface
The on-board I2C components are connected to MIO10 and MIO11 and configured as I2C0 by default.
I2C addresses for on-board components:
| Device | I2C-Address | Notes |
|---|---|---|
| EEPROM for MAC1 | 0x50 | |
| EEPROM for MAC2 | 0x81 | |
| EEPROM for MAC3 | 0x82 | |
| RTC | ||
| Battery backed RAM | integrated in RTC |
B2B I/O
Number of I/O's connected to the SoC's I/O bank and B2B connector:
| Bank | Type | Jx | IO count | IO Voltage | Notes |
|---|---|---|---|---|---|
| 500 | MIO | J2-87 J2-88 | 2 | 3,3 V | |
| 500 | MIO | J2-93 J2-95 J2-94 J2-96 | 4 | 3,3 V | configured as I2C1 and USART0 by default, configurable as GPIO by user |
| 13 | HR | J1 | 48 | user | |
| 33 | HR | J1 | 48 | user | |
| 35 | HR | J2 | 30 | 3,3 V |
For detailed information about the pin out, please refer to the Master Pinout Table.
Peripherals
LED's
There are 3 LED's on TE0729:
| LED | Color | Connected to | Notes |
|---|---|---|---|
| D1 | red | System Controller | Global Status LED |
| D2 | green | DONE | Inverted DONE, ON when FPGA not configured |
| D8 | red | MIO7 | OFF when PS7 not booted and not controlling MIO7 by software, else user controlled |
LED D2 is connected to the FPGA Done pin and will go off as soon as PL is configured.
This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module.
Ethernet
The TE0715 is populated with a Marvell Alaska 88E1512 Gigabit Ethernet PHY. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling.
SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3.
The reference clock input of the PHY is supplied from an on board 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
PHY connection:
| MDC/MDIO | MIO52, MIO53 | - | - |
| LED0 | - | J3 | can be routed via PL to any free PL I/O pin in B2B connector |
| LED1 | - | K8 | can be routed via PL to any free PL I/O pin in B2B connector |
| LED2/Interrupt | MIO46 | - | - |
| CONFIG | - | - | By default the PHY Address is strapped to 0x00 alternate configuration is possible |
| RESETn | MIO50 | - | - |
| RGMII | MIO16..MIO27 | - | - |
| SGMII | - | - | on B2B |
| MDI | - | - | on B2B |
Note: LED1 is connected to PL via level-shifter implemented in system controller CPLD.
USB
The USB PHY USB3320 from Microchip is used on the TE0715. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.
The reference clock input of the PHY is supplied from an on board 52MHz oscillator (U15).
PHY connection:
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY |
| REFCLK | - | - | 52MHz from on board oscillator (U15) |
| REFSEL[0..2] | - | - | 000 GND, select 52MHz reference Clock |
| RESETB | MIO51 | - | Active low reset |
| CLKOUT | MIO36 | - | Connected to 1.8V selects reference clock operation mode |
| DP,DM | - | OTG_D_P, OTG_D_N | USB Data lines |
| CPEN | - | VBUS_V_EN | External USB power switch active high enable signal |
| VBUS | - | USB_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
| ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating |
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC
An Intersil temperature compensated real time clock IC ISL12020M is used for timekeeping (U16). Battery voltage must be supplied to the module from the main board.
Battery backed registers are accessed at I2C slave address 0x6F.
General purpose RAM is accessed at I2C slave address 0x57.
This RTC IC is supported in Linux so it can be used as hwclock device.
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