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Main Components

1. Xilinx Zynq UltraScale+ MPSoC-7000 SoC, U1
2. Lattice Semiconductor MachXO2 1200HC CPLD, U14
3. 4Gbit DDR3L SDRAM, U19
4. 4Gbit DDR3L SDRAM, U10
5. I²C voltage translator, U25
6. Intersil ISL12020MIRZ Real Time Clock, U17
7. Microchip USB3320C USB PHY transceiver, U4
8. Microchip USB3320C USB PHY transceiver, U8
9. SiTime SiT8008 52.000000 MHz oscillator, U7
10. 32 MByte QSPI Flash memory, U38
11. SiTime SiT8008 33.333333 MHz oscillator, U61
12. SI5338A programmable quad PLL clock generator, U2
13. SiTime SiT8008 25.000000 MHz oscillator, U3
14. TPS74801 LDO @1.5V, U23
15. LT quad 4A PowerSoC DC-DC converter (@1.0V), U13
16. LT quad 4A PowerSoC DC-DC converter (@3.3V, @1,8V, @1.2V_MGT, @1.0V_MGT), U16
17. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J2
18. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J3
19. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J1
20. Marvell Alaska 88E1512 Gigabit Ethernet PHY, 20
    
21. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U18
22. Micron Technology 4 GByte eMMC, U15
23. Microchip 128Kbit I²C EEPROM, U26
24. Microchip 2Kbit I²C MAC EEPROM, U24
25. Microchip 2Kbit I²C MAC EEPROM, U22
26. TPS51206 DDR reference voltage and termination regulator, U6
27. TPS799 LDO @1.8V_MGT, U5
28. SiTime SiT8008 25.000000 MHz oscillator, U11

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4 of the 7 boot mode strapping pins (MIO2 ... MIO8) of the Xilinx Zynq-7000 SoC device are hardware programmed on the board, 3 of them are set be by the SC CPLD firmware. They The boot strapping pins are evaluated by the Zynq device soon after the 'PS_POR' signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).

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The Xilinx Zynq-7000 SoC used on the TE0782 module has 16 MGT transceiver lanes. All of them are wired directly to B2B connectors J1 and J3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane with data transmission rates up to 12.5Gb/s per lane (Xilinx GTX transceiver). Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Board to

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Table 11: General overview of the Gigabit Ethernet2 USB0 PHY signals

USB1 PHY connection:

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Table 12: General overview of the Gigabit Ethernet2 USB1 PHY signals

I2C Interface

The on-board I²C components are connected to bank 35 pins L15 (I2C_SDA) and L14 (I2C_SCL).

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eMMC Flash memory device (U15) is connected to the Zynq PS MIO bank 500 pins MIO10..MIO15. eMMC chips MTFC4GMVEA-4M IT (Flash NAND-IC 2x 16 Gbit) is used with 4 GByte of memory density.

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DDR3L Memory

By default TE0782-02 module has two 16-bit wide IM (Intelligent Memory) IM4G16D3FABG-125I DDR3L SDRAM (DDR3-1600 Speedgrade) chips (U10, U19) arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM.

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Two quad SPI compatible serial bus flash memory for FPGA configuration file storage is provided by Spansion S25FL256SAGBHI20 (U38) with 256 Mbit (32 MByte) memory density. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

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Power supply with minimum current capability of 3A 4A for system startup is recommended.

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Table 17: Power consumption

 * TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

The Trenz TE0782 SoM is equipped with two quad DC-DC voltage regulators to generate required on-board voltage levels 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT. Additional voltage regulators are used to generate voltages 1.5V, VTT, VTTREF and 1.8V_MGT.

The power supply voltage 'C3.3V' of System Controller CPLD of the SoM have to be externally supplied with 3.3V nominal.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

See also Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0782 module.

Power-On Sequence

The TE0820 SoM meets the recommended criteria to power up the Xilinx Zynq chip properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Power-on sequence is handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

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It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.

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Power Rails

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Table 19: Module I/O bank voltages

See Xilinx Zynq-7000 datasheet DS191 for the voltage ranges allowed.

Board to Board Connectors

The TE0782 SoM has three 160-pin double-row ASP-122952-01  Samtec connectors on the bottom side which mate with ASP-122953-01 Samtec connectors on the baseboard. Mating height is 5 mm.

-7000 datasheet DS191 for the voltage ranges allowed.

Board to Board Connectors

Variants Currently In Production

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