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The boot modes are controlled by the Pins Pin 'BOOTMODE' and '?' on the board to board (B2B) connector.
BOOTMODE | ?Boot mode | |
|---|---|---|
| LOW | LOW?? | JTAGLOW |
| HIGH ?? | SPI (also eMMC as secondary boot) | |
| HIGH | LOW | |
| HIGH | HIGH |
JTAG
JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.
| Signal | B2B Pin |
|---|---|
| TCK | J3: 141 |
| TDI | J3: 147 |
| TDO | J3: 148 |
| TMS | J3: 1142 |
| Note |
|---|
JTAGENB pin in J2 should be kept low or grounded for normal operation. |
Clocking
CPLD-JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.
| Signal | B2B Pin |
|---|---|
| M_TCK | J3: 81 |
| M_TDI | J3: 87 |
| M_TDO | J3: 82 |
| M_TMS | J3: 88 |
| Note |
|---|
JTAGENB pin in J2 should be kept low or grounded for normal operation. |
Clocking
| Clock | Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|---|
| PS CLK | 33.3333 MHz | U61 | PS_CLK | PS Subsystem main clock | |
| 10/100/1000 Mbps ETH PHYs reference | 25 MHz | U11 | - | ||
| USB PHY reference | 52 MHz | U7 | - | ||
PLL reference | 25 MHz | U3 | - | ||
GT REFCLK1 | - | B2B | AC7/AC8 | Externally supplied from base | |
GT REFCLK4 | - | B2B | U7/U8 | Externally supplied from base | |
quad programmable clock (I2C) SI5338A | user | U2 | - | GT REFCLK0 GT REFCLK3 GT REFCLK5 GT REFCLK6 |
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| MIO | Configured as | B2B | Notes | ||||
|---|---|---|---|---|---|---|---|
| 0GPIO | OTG-RST33 | J2 -87 | B2Bconnected to CPLD | ||||
| 1 | QSPI0 | - | SPI Flash-CS | ||||
| 2 | QSPI0 | - | SPI Flash-DQ0 | ||||
| 3 | QSPI0 | - | SPI Flash-DQ1 | ||||
| 4 | QSPI0 | - | SPI Flash-DQ2 | ||||
| 5 | QSPI0 | - | SPI Flash-DQ3 | ||||
| 6 | QSPI0 | - | SPI Flash-SCK | ||||
| 7GPIO | ETH1_RESET33 | -Red | LED D8connected to CPLD | ||||
| 8 | GPIO | - | - | QSPI feedback clockconnected to CPLD and Pull-Up 3.3V | |||
| 9 | GPIO | J2-88 | B2Bconnected to CPLD | ||||
| 10I2C0 SDA | MMC-D0 | J2-90 | B2B - | ||||
| 11I2C0 SCL | MMC-CMD | J2-92 | B2B- | ||||
| 12I2C1 SDA | MMC-CCLK | J2-93 | B2B (SDA on-board I2C, also configurable as GPIO by user) | ||||
| 13 | I2C1 SCL | J2-95 | B2B (SCL on-board I2C, also configurable as GPIO by user) | ||||
| 14 | USART0 RX | J2-94 | B2B (RX on-board UART, also configurable as GPIO by user) | ||||
| 15 | USART0 TX | J2-96 | B2B (TX on-board UART, also configurable as GPIO by user) | ||||
| 16..27 | ETH0 | Ethernet RGMII PHY | |||||
| 28..39 | USB0 | USB ULPI PHY | |||||
| 40 | SDIO0 | J2-100 | |||||
| 41 | SDIO0 | J2-102 | |||||
| 42 | SDIO0 | J2-104 | |||||
| 43 | SDIO0 | J2-106 | |||||
| 44 | SDIO0 | J2-108 | |||||
| 45 | SDIO0 | J2-110 | |||||
| 46 | GPIO | - | RTC Interrupt | ||||
| 47 | - | - | - | ||||
| 48 | GPIO | SEL_SD | SD Card multiplexer control | ||||
| 49 | GPIO | - | USB Reset | ||||
| 50 | GPIO | - | ETH0 Interrupt | ||||
| 51 | GPIO | - | ETH0 Reset | ||||
| 52 | ETH0 | - | MDC | ||||
| - | |||||||
| 13 | MMC-D1 | - | - | ||||
| 14 | MMC-D2 | - | - | ||||
| 15 | MMC-D3 | - | - | ||||
| 16..27 | ETH0 | - | Ethernet RGMII PHY | ||||
| 28..39 | USB0 | - | USB0 ULPI PHY | ||||
| 40...51 | USB1 | - | USB1 ULPI PHY | ||||
| 52 | ETH0 MDC | - | - | ||||
| 53 | ETH0 MDIO | - | - | 53 | ETH0 | - | MDIO
I2C Interface
The on-board I2C components are connected to IO_L1P_T0AD0P_35 BANK35, Pin L15 (I2C_SDA and) IO_L1N_T0AD0N_35 ) and to BANK35, Pin L14 (I2C_SCL).
I2C addresses for on-board components
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