Page History
...
- 2 x Gbps Ethernet PHY transceiver
- 16-Bit wide 2 x 512 MByte DDR3 SDRAM
- 32 MByte QSPI Flash Memory for configuration, operation and to store data
- eMMC (4 GByte in standard configuration)
- 2 x USB PHY transceiver
- 16 GTX high-performance transceiver lanes
- powerful switch-mode power supplies for all on-board voltages
- large number of configurable I/Os is provided via rugged high-speed stacking strips
...
| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
| PS CLK | 33.3333 MHz | U61 | PS_CLK | PS Subsystem main clock |
| 10/100/1000 Mbps ETH PHYs reference | 25 MHz | U11 | - | |
| USB PHY reference | 52 MHz | U7 | - | |
PLL reference | 25 MHz | U3 | - | |
GT REFCLK1 | - | B2B connector | AC7/AC8 | Externally supplied from base |
GT REFCLK4 | - | B2B connector | U7/U8 | Externally supplied from base |
quad programmable clock (I2C) SI5338A | user | U2 | - | GT REFCLK0 GT REFCLK3 GT REFCLK5 GT REFCLK6 |
...
| Peripheral | IC | Designator | PS | MIO | Notes | ||
|---|---|---|---|---|---|---|---|
| QSPI Flash | S25FL256SAGBHI20 | U38 | QSPI0 | MIO1...MIO6 | - | ||
| Ethernet0 10/100/1000 Mbps PHY | 88E1512-A0-NNP2I000 | U18 | ETH0; GPIO BANK35 | MIO16...MIO27, MIO52, MIO53 | - | ||
| Ethernet0 10/100/1000 Mbps PHY Reset | GPIO | MIO7 | ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET | ||||
| Ethernet1 10/100/1000 Mbps PHY | 88E1512-A0-NNP2I000 | U20 | GPIO BANK9, BANK35 | - | - | ||
| Ethernet1 10/100/1000 Mbps PHY Reset | GPIO BANK35, Pin B15 | - | - | ||||
| USB0 | USB3320C-EZK | U4 | USB0 | MIO28...MIO39 | - | ||
| USB0 Reset | GPIO | MIO0 | OTG_RESET33 (MIO0) -> CPLD -> OTG_RESET | ||||
| USB1 | USB3320C-EZK | U8 | USB1 | MIO40...MIO51 | - | ||
| USB1 Reset | GPIO | MIO0 | OTG_RESET33 (MIO0) -> CPLD -> OTG_RESET | ||||
| Clock PLL | Si5338 | U2 | I2C | BANK35, Pin L14/L15 | Low jitter phase locked loop | ||
| e-MMC (embedded e-MMC) | MTFC4GMVEA-4M IT | U15 | SDIO0 | MIO10...MIO15 | - | ||
| HyperFlash RAM | S26KS512SDPBHI00x | U9 | GPIO BANK35 | - | optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM) optional 2 x 32 MByte HyperFLASH | ||
| HyperFlash RAM | S26KS512SDPBHI00x | U12 | GPIO BANK35 | - | as above | ||
| EEPROM I2C | 24LC128-I/ST | EEPROM I2C | 24LC128-I/ST | U26 | GPIO BANK35, Pin L14/L15 | - | - |
| EEPROM I2C | 24AA025E48T-I/OT | U22 | GPIO BANK35, Pin L14/L15 | - | MAC Address | ||
| EEPROM I2C | 24AA025E48T-I/OT | U24 | GPIO BANK35, Pin L14/L15 | - | MAC Address | ||
| RTC | ISL12020MIRZ | U17 | GPIO BANK35, Pin L14/L15 | - | Temperature compensated real time clock | ||
| RTC Interrupt | ISL12020MIRZ | U17 | - | - | RTC_INT -> CPLD |
...
| Device | IC | Designator | I2C-Address | Notes |
|---|---|---|---|---|
| EEPROM | 24LC128-I/ST | U26 | 0x53- | user data, parameter |
| EEPROM | 24AA025E48T-I/OT | U22 | 0x50 | MAC Address |
| EEPROM | 24AA025E48T-I/OT | U24 | 0x51 | MAC Address |
| RTC | ISL12020MIRZ | U17 | 0x6F | Temperature compensated real time clock |
| Battery backed RAM | ISL12020MIRZ | U17 | 0x57 | integrated in RTC |
| CLOCK GENERATORPLL | SI5338A-B-GMR | U2 | 0x70 | Quad reference clock for GTX transceiver lanes |
| CPLD | LCMXO2-1200HC-4TG100I | U14 | user | - |
...
The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11).
...
| PHY PIN | ZYNQ PS | System Controller CPLD | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| LED0 | Bank35BANK35, Pin B12 | - | - |
| LED1 | Bank35BANK35, Pin C12 | - | - |
| Interrupt | Bank35BANK35, Pin A15 | - | - |
| CONFIG | Bank35BANK35, Pin F14 | - | - |
| RESETn | - | Pin 53 | ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET |
| RGMII | MIO16..MIO27 | - | |
| MDI | - | - | on B2B J2 connector |
...
| PHY PIN | ZYNQ PS | System Controller CPLD | Notes |
|---|---|---|---|
| MDC/MDIO | Bank35BANK35, Pin C17/B17 | - | - |
| LED0 | Bank35BANK35, Pin K15 | - | - |
| LED1 | Bank35BANK35, Pin B16 | - | - |
| Interrupt | Bank35BANK35, Pin A17 | - | - |
| CONFIG | Bank35BANK35, Pin E15 | - | Pin connected to GND, PHY Address is strapped to 0x00 by default |
| RESETn | Bank35BANK35, Pin B15 | - | - |
| RGMII | Bank9BANK9 | - | - |
| MDI | - | - | on B2B J2 connector |
USB
The TE0782 is equipped with two USB PHY PHYs USB3320 from Microchip is used on the TE0729 (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.
The reference clock input of the PHY both PHYs is supplied from an on board 52MHz oscillator (U12U7).
USB0 PHY connection:
| PHY Pin | Zynq Pin | CPLD | B2B Name (J2) | Notes |
|---|---|---|---|---|
| ULPI | MIO28..39 | - | - | Zynq USB0 MIO pins are connected to the PHY |
| REFCLK | - | - | - | 52MHz from on board oscillator (U12U7) |
| REFSEL[0..2] | - | - | - | 000 GND, select 52MHz reference Clock |
| RESETB | MIO0MIO49 | OTG_RESET33 | -Active low reset | OTG_RESET33 -> CPLD -> OTG_RESET |
| CLKOUT | MIO36 | - | - | Connected to 1.8V selects reference clock operation mode |
| DP,DM | - | - | OTGUSB1_D_P, OTGUSB1_D_N | USB Data lines |
| CPEN | - | - | VBUS1VBUS_V_EN | External USB power switch active high enable signal |
| VBUS | - | - | USB1USB_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
| ID | - | - | OTGOTG1_ID | For an A-Device connect to ground, for a B-Device left floating |
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC
An Intersil temperature compensated real time clock IC ISL12020MIRZ is used for timekeeping (U22). Battery voltage must be supplied to the module from the main board.
Battery backed registers are accessed at I2C slave address 0x57.
General purpose RAM is accessed at I2C slave address 0x6F.
This RTC IC is supported in Linux so it can be used as hwclock device.
MAC-Address EEPROMs
Three Microchip 24AA025E48 EEPROMs (U8, U9, U20) are used on the TE0729. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50 for MAC-Address1 (U8), 0x81 for MAC-Address2 (U9), 0x82 for MAC-Address3 (U20).
Power
For startup, a power supply with minimum current capability of 3A is recommended.
VIN and 3.3VIN can be connected to the same source (3.3 V).
Power Supplies
Supply Voltage | Voltage Range | note |
|---|---|---|
Vin | 3.3 V to 5.5 V | Typical 200 mA, depending on customer design and connections |
| Vin 3.3V | 3.3 V | Typical 50 mA, depending on customer design and connections |
Bank Voltages
USB1 PHY connection:
| PHY Pin | Zynq Pin | CPLD | B2B Name (J2) | Notes |
|---|---|---|---|---|
| ULPI | MIO40..51 | - | - | Zynq USB1 MIO pins are connected to the PHY |
| REFCLK | - | - | - | 52MHz from on board oscillator (U7) |
| REFSEL[0..2] | - | - | - | 000 GND, select 52MHz reference Clock |
| RESETB | MIO0 | OTG_RESET33 | - | OTG_RESET33 -> CPLD -> OTG_RESET |
| CLKOUT | MIO48 | - | - | Connected to 1.8V selects reference clock operation mode |
| DP,DM | - | - | USB2_D_P, USB2_D_N | USB Data lines |
| CPEN | - | - | VBUS2_V_EN | External USB power switch active high enable signal |
| VBUS | - | - | USB2_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
| ID | - | - | OTG2_ID | For an A-Device connect to ground, for a B-Device left floating |
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC
An Intersil temperature compensated real time clock IC ISL12020MIRZ is used for timekeeping (U17). Battery voltage must be supplied to the module from the main board.
Battery backed registers are accessed at I2C slave address 0x57.
General purpose RAM is accessed at I2C slave address 0x6F.
This RTC IC is supported in Linux so it can be used as hwclock device.
PLL
The TE0782 is also equipped with a Silicon Labs I2C-programmable clock generator Si5338A (U2). The Si5338 can be programmed using the I2C-bus, to change the frequency on its outputs. It is accessible on the I2C slave address 0x70.
PLL connection:
Input/Output | Default Frequency | Notes |
|---|---|---|
| IN1/IN2 | Externally supplied | need decoupling on base board |
IN3 | 25MHz | Fixed input clock |
IN5 | - | not available and not used |
IN4/IN6 | - | connected to Ground |
CLK0 A/B | - | GT REFCLK0 |
CLK1 A/B | - | GT REFCLK3 |
CLK2 A/B | - | GT REFCLK6 |
CLK3 A/B | - | GT REFCLK5 |
MAC-Address EEPROMs
Two Microchip 24AA025E48 EEPROMs (U22 and U24) are used on the TE0782. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. Those are accessible by the I2C slave address 0x50 for MAC-Address1 (U22), 0x51 for MAC-Address2 (U24) .
Power
For startup, a power supply with minimum current capability of 3A is recommended.
VIN and 3.3VIN can be connected to the same source (3.3 V).
Power Supplies
Supply Voltage | Voltage Range | note |
|---|---|---|
Vin | 3.3 V to 5.5 V | Typical 200 mA, depending on customer design and connections |
| Vin 3.3V | 3.3 V | Typical 50 mA, depending on customer design and connections |
Bank Voltages
| Bank | Voltage | max. Value | note | ||||
|---|---|---|---|---|---|---|---|
| 0 | 3,3 V | - | FPGA Configuration | ||||
| 502 | 1,5 V | - | DDR3-RAM Port | ||||
| 109 / 110 / 111 / 112 | 1,2 V | - | FPGA MGT | ||||
| 500 / 501 | 3,3 V | - | MIO Banks | ||||
| 9 | 1,8 V | - | ETH2 RGMII | ||||
| 10 | user | 3,3 V | B2B name: VCCIO_10 | ||||
| 11 | user | 3,3 V | B2B name: VCCIO_11 | ||||
| 12 | user | 3,3 V | B2B name: VCCIO_12 | ||||
| 13 | user | 3,3 V | B2B name: VCCIO_13 | ||||
| Bank | Voltage | max. Value | note | ||||
| 501 | 1,8 V | - | ETH0 / USB0 / SDIO0 | ||||
| 500 | 3,3 V | - | SPI / I2C / UART | ||||
| 502 | 1,5 V | - | DDR3-RAM | ||||
| 13 | user | 3,3 V | connected to 3,3V by default by 0-Ohm-Resistor R36 | ||||
| 33 | user | 3,3 V | connected to 3,3V by default by 0-Ohm-Resistor R55 | ||||
| 34 | 2,5 V | - | ETH / DISP | ||||
| B2B name: VCCIO_33 | |||||||
| 34 | user | 3,3 V | B2B name: VCCIO_34 | ||||
| 35 | 1,8 V | - | Hyper-RAM, Ethernet, I2C | 35 | 3,3 V | - | GPIO |
Initial Delivery state
| Storage device name | Content | Notes |
|---|---|---|
| 24LC128-I/ST | not programmed | User content |
24AA025E48 EEPROMs | User content not programmed | Valid MAC Address from manufacturer |
| e-MMC Flash-Memory | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
| HyperFlash RAM | not programmed | |
EFUSE USER | Not programmed | |
EFUSE Security | Not programmed |
...
| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
Vin supply voltage | -0.3 | 6.0 | V | |
Vin33 supply voltage | -0.4 | 3.6 | V | |
| VBat supply voltage | -1 | 6.0 | V | |
| PL IO Bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | |
| I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0729 TE0782 does not have HP banks |
Voltage on Module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal |
Storage Temperature | -40 | +85 | C | |
| Storage Temperature without the ISL12020MIRZ | -55 | +100 | C |
...
| date | revision | authors | description |
|---|---|---|---|
| 20062016-06-1427 | v10 | initial release |
Disclaimer
...
Overview
Content Tools