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On https://wiki.trenz-electronic.de/display/PD/TE0782-02+TRM the online version of this manual and other documents can be found.
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The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC. It is equipped with a Xilinx Zynq-7 (XC7Z035, XC7Z045 or XC7Z100).

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  • 2 x Gbps Ethernet PHY transceiver
  • 32-Bit DDR3 SDRAM 1Gbyte
  • 32 MByte QSPI Flash Memory for configuration, operation and to store data
  • eMMC (4 GByte in standard configuration)
  • 2 x USB PHY transceiver
  • 16 GTX high-performance transceiver lanes
  • powerful switch-mode power supplies for all on-board voltages
  • large number of configurable I/Os is provided via rugged high-speed stacking strips

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Diagram

Key Features

  • Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoM
  • Rugged for shock and high vibration
  • Dual ARM Cortex-A9 MPCore
    • 1 GByte DDR3 SDRAM (2 x 16RAM (32-Bit wide 512 MByte DDR3 SDRAM)
    • 32 MByte QSPI Flash memory
    • 2 x Hi-Speed USB2.0 ULPI transceiver PHY
    • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
    • 4 GByte eMMC (optional up to 64GByte)
  • 2 x MAC-Address EEPROMs
  • optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM) or optional 2 x 64 MByte HyperFLASH
  • Temperature compensated RTC (real-time clock)
  • Si5338 PLL for GTX Transceiver clocks
  • Plug-on module with 3 x 160-pin high-speed strips
    • 16 GTX high-performance transceiver lanes
    • GT transceiver clock inputs
    • 254 FPGA I/O's (125 LVDS pairs)
  • On-board high-efficiency DC-DC converters
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
  • User LED

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NameNote
BOOTMODEuser configurable (CPLD)
CONFIGXuser configurable (CPLD)
JTAGENBJTAG operationspecial mode pin for SC CPLD
RESINSystem-reset
CLPD_GPIO0user GPIOFunction defined by CPLD Firmware
CLPD_GPIO1user GPIOFunction defined by CPLD Firmware
CLPD_GPIO2user GPIOFunction defined by CPLD Firmware
CLPD_GPIO3user GPIOFunction defined by CPLD Firmware
CLPD_GPIO4user GPIOFunction defined by CPLD Firmware
CLPD_GPIO5Function defined by CPLD Firmware
CLPD_GPIO6 
CLPD_GPIO7 user GPIO

Small CPLD controls some functions of the SoM, this CPLD can be updated by the end user if support is designed in on customer base.

Boot Modes

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Silabs Multisynth PLL Si5338 can deliver GT reference clocks to all 4 GT Banks. Additionally a GT Reference clock can be generated on the base board for any of the 4 GT Banks. There is reference clock available on the TE0782 for Si5338, there is no need to supply a master optionally external reference clock can be supplied from the base.

ClockFrequencyICZYNQ PS / PLNotes
PS CLK33.3333 MHzU61BANK500, PS _ CLKPS Subsystem main clock
10/100/1000 Mbps ETH PHYs reference25 MHzU11- 
USB PHY reference52 MHzU7- 

PLL reference

25 MHz

U3

-

 

GT REFCLK1

-

B2B connector

BANK110, Pin AC7/AC8

Externally supplied from base

GT REFCLK4

-

B2B connector

BANK111, Pin U7/U8

Externally supplied from base

Si5338 CLK0 

quad programmable clock (I2C)

SI5338A

userU2BANK110, Pin AA8/AA7?
Si5338 CLK1 U2BANK109, Pin AF10/AF9?
Si5338 CLK2 U2BANK111, Pin W8/W7?
Si5338 CLK3 U2BANK112, Pin N8/N7

GT REFCLK0

GT REFCLK3

GT REFCLK5

GT REFCLK6

?

Processing System (PS) Peripherals

PeripheralICDesignatorZYNQ PS / PLMIONotes
QSPI FlashS25FL256SAGBHI20U38PS QSPI0MIO1...MIO6-
ETH0 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U18PS ETH0; GPIO BANK35MIO16...MIO27, MIO52, MIO53-
ETH0 10/100/1000 Mbps PHY Reset  PS GPIOMIO7ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET
ETH1 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U20GPIO BANK9, BANK35-PHY can be used with soft Ethernet MAC IP also
ETH1 10/100/1000 Mbps PHY Reset  GPIO BANK35, Pin B15--
USB0USB3320C-EZKU4PS USB0MIO28...MIO39-
USB0 Reset  PS GPIOMIO0OTG_RESET33 (MIO0) -> CPLD -> OTG_RESET
USB1USB3320C-EZKU8USB1MIO40...MIO51-
USB1 Reset  PS GPIOMIO0OTG_RESET33 (MIO0)  -> CPLD -> OTG_RESET
Clock PLLSi5338U2I2CBANK35, Pin L14/L15 Low jitter phase locked loop
 e-MMC (embedded e-MMC)MTFC4GMVEA-4M IT  U15SDIO0MIO10...MIO15-
HyperFlash RAMS26KS512SDPBHI00xU9GPIO BANK35-

optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM)

or optional 2 x 64 MByte HyperFLASH

HyperFlash RAMS26KS512SDPBHI00xU12GPIO BANK35-as above
EEPROM I2C24LC128-I/STU26GPIO BANK35, Pin L14/L15--
EEPROM I2C24AA025E48T-I/OTU22GPIO BANK35, Pin L14/L15-MAC Address
EEPROM I2C24AA025E48T-I/OTU24GPIO BANK35, Pin L14/L15-MAC Address
RTCISL12020MIRZU17GPIO BANK35, Pin L14/L15-Temperature compensated real time clock
RTC InterruptISL12020MIRZU17--RTC_INT -> CPLD

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MIOConfigured asB2BNotes
0OTG-RST33USB Reset -connected to CPLD used as level translator
1QSPI0 -SPI Flash-CS
2QSPI0 -SPI Flash-DQ0
3QSPI0 -SPI Flash-DQ1
4QSPI0 -SPI Flash-DQ2
5QSPI0 -SPI Flash-DQ3
6QSPI0 -SPI Flash-SCK
7ETH1_RESET33Ethernet Reset -connected to CPLD used level translator
8,GPIOUART-connected to CPLD and Pull-Up 3.3V 
9GPIOUART-connected to CPLD 
10MMC-SDIO1 D0--
11MMC-SDIO1 CMD--
12MMC-CCLKSDIO1 CLK--
13MMC-SDIO1 D1--
14MMC-SDIO1 D2--
15MMC-SDIO1 D3--
16..27ETH0-Ethernet RGMII PHY
28..39USB0-USB0 ULPI PHY
40...51USB1-USB1 ULPI PHY
52ETH0 MDC--
53ETH0 MDIO--

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DeviceICDesignatorI2C-AddressNotes
EEPROM24LC128-I/STU260x53user data, parameter
EEPROM24AA025E48T-I/OTU220x50MAC Address/EEPROM
EEPROM24AA025E48T-I/OTU240x51MAC Address/EEPROM
RTCISL12020MIRZU170x6FTemperature compensated real time clock
Battery backed RAMISL12020MIRZU170x57integrated in RTC
PLLSI5338A-B-GMRU20x70Quad reference clock for GTX transceiver lanes 
CPLDLCMXO2-1200HC-4TG100IU14user-

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Number of I/O's connected to the SoC's I/O bank and B2B connector

BankTypeVCCIO MaxB2BConnectorIO countDifferentíalIO VoltageNotes
10HR3.3VJ34422user22 LVDS-pairs possible 
11HR3.3VJ34020user20 LVDS-pairs possible 
12HR3.3VJ24020user20 LVDS-pairs possible 
13HR3.3VJ24020user20 LVDS-pairs possible 
33HRHP1.8VJ14823user23 LVDS-pairs possible 
34HRHP1.8VJ14220user20 LVDS-pairs possible 

For detailed information about the pin out, please refer to the Master Pinout Table.

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Frequency of LED-Toggling [1/2.6sec]Status
1Power problem
2MGT Power problem
3Reset from mainboardbase board
4FPGA not programmed

This function depend on the CPLD revision.

D2 - On- Onboard board GREEN LED

Green LED connected to MIO8

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PHY PINZYNQ PS / PLSystem Controller CPLDNotes
MDC/MDIOBANK35, Pin C17/B17--
LED0BANK35, Pin K15--
LED1BANK35, Pin B16--
InterruptBANK35, Pin A17--
CONFIGBANK35, Pin E15-Pin connected to GND, PHY Address is strapped to 0x00 by default
RESETnBANK35, Pin B15--
RGMIIBANK9--
MDI-

-

on B2B J2 connector-

 

USB

The TE0782 is equipped with two USB PHYs USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

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not available and not used

Input/Output

Default Frequency

Notes

IN1/IN2

Externally supplied

need decoupling on base board

IN3

25MHz

Fixed input clock

IN5

-

IN4/IN6

-

connected to Ground

CLK0 A/B

-

GT REFCLK0

CLK1 A/B

-

GT REFCLK3

CLK2 A/B

-

GT REFCLK6

CLK3 A/B

-

GT REFCLK5

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BankVoltagemax. Valuenote
03,.3 V-FPGA Configuration
5021,.5 V-DDR3-RAM Port
109 / 110 / 111 / 1121,.2 V-FPGA MGT
500 / 5013,.3 V-MIO Banks
91,.8 V-ETH2 RGMII
10user3,.3 VB2B name: VCCIO_10
11user3,.3 VB2B name: VCCIO_11
12user3,.3 VB2B name: VCCIO_12
13user3,.3 VB2B name: VCCIO_13
33user3,3 1.8 VB2B name: VCCIO_33
34user3,3 1.8 VB2B name: VCCIO_34
351,.8 V-Hyper-RAM, Ethernet, I2C

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ParameterMinMaxUnitsNotes

Vin supply voltage

-0.36.0

 

V

 

Vin33 supply voltage

-0.43.6

 

V

 
VBat supply voltage-16.0 V 
PL IO Bank supply voltage for HR I/O banks (VCCO)-0.53.6V 
I/O input voltage for HP I/O banks-0.55VCCO_X+0.55VTE0782 does not have HP banks 

Voltage on Module JTAG pins

-0.4

VCCO_0+0.55

V

VCCO_0 is 3.3V nominal

Storage Temperature

-40

+85

C

 
Storage Temperature without the ISL12020MIRZ-55+100C 

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ParameterMinMaxUnitsNotesReference document
Vin supply voltage2.5  5.5V  
Vin33 supply voltage3.135  3.465V  
VBat supply voltage2.7  5.5V  
PL IO Bank supply voltage for HR I/O banks (VCCO)1.143.465V Xilinx document DS191
I/O input voltage for HR I/O banks(*)(*)V(*) Check datasheetXilinx document DS191 and DS187
      
Voltage on Module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal 

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All dimensions are shown in mm.

 

WeigtWeight

Part

60 g

Plain module

Temperature Ranges

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