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The usage of this steps is at owner's own risk. Trenz Electronic is not liable for damage caused by following this steps.
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The Xilinx tools do not handle DDR-Less Design correctly, to get around this "bug" manual modifications are necessary, see DDR less ZYNQ Design. It should be fixed or make a little bit confortable by Xilinx but until Vivado 2016.2 it's not done. |
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Procedure
For this case, you can try the following steps without guarantee for success:
- Close all Xilinx Programs.
- Power off TE0722
- Bridge S25FL127S Pin 7 temporary with GND to set Boot Mode to independent JTAG (See picture xxx).
- Power on TE0722
- Open SDK
- Disconnect you GND bridge to Pin 7
- (optional) Try to get access to the FPGA with SDK Debugger (Is this not possible, flash programming is also not possible)
- Try to program Flash with valid Boot.Bin, if programming failed try again from step 1.
GND-Bridge to S25FL127S Pin 7
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Connect Pin 7 to Pin 4 (GND) only temporary for startup procedure. After startup, Pin 7 trace is used to program the Flash. So you must disconnect your GND-bridge.
References
- Zynq-7000 All Programmable SoC - Technical Reference Manual (UG585):Page 167-Section 6.25 Boot Mode Pin Settings
- TE0722 Schematics:TE0722 Download Page
- S25FL127SABMFV10 Datasheet
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