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[TE USB Suite]
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TE USB FX2 Suite
TE USB FX2 Technology Stack Overview
Logic Architecture Layer (Generation 2 = Generation 3): FPGA image
Preloaded Logic Architecture Layer (in SPI Flash): Reference Architecture Layer description
TO DELETE XPS_NPI_DMA custom IP core block
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Old Version
10
changes.mady.by.user
Sergio Pavesi
Saved on
14 09, 2016
compared with
New Version
11
changes.mady.by.user
Sergio Pavesi
Saved on
14 09, 2016
Previous Change: Difference between versions 9 and 10
Next Change: Difference between versions 11 and 12
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Read Jumps Register (RJR)
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Status Register (SR)
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wr_xfer_counter
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Read Address Counter Register (RCR)
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rd_xfer_counter
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Interrupt registers
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Conection of user logic interrupt to INTR_IPIER and INTR_IPISR.
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Programmin model
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Overview
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