TO DELETE XPS_NPI_DMA custom IP core block

Description

XPS_NPI_DMA is high performance direct memory access (DMA) engine which seamlessly integrates into Xilinx EDK environment (figure below). It is highly flexible due to full access of the softcore MicroBlaze to the XPS_NPI_DMA core functionality through 9 32-bit registers attached to PLBv4.6 bus.

It enables high speed data streaming to (input port) and from (output port) an external memory attached to a Xilinx Multiport Memory Controller (MPMC).

Features

• The input and output port can run simultaneously.
• The transfer on each port can have its own allocated memory space and can be looped. Loop means that when the transfer will run indefinitely on allocated memory space (like a frame buffer) until stopped.
• The data written to the input port can be stored in a memory linearly.
• The data coming out from the output port can be read in X-Y pattern. That means it can read data linearly or canjump in memory locations to transpose input data – used for rotating image for 90 degrees. That is possible when using single beat transactions (word or double-word) for reading.

The XPS_NPI_DMA has 4 interfaces:

• Xilinx PLBv4.6 created with IPIF wizard for access to 9 x 32-bit registers. These registers control the whole peripheral operation.
• MPMC Native Port Interface (NPI) bus supporting 32 or 64-bit width. This bus is used for highspeed access to external memory.
• Proprietary synchronous 32 or 64-bit wide DMA_IN bus used for data streaming to external memory. This port can stream data in blocks – up to 64 word burst (64-bit only). Maximal sustainable bandwidth at 100MHz NPI_Clk is 200MB/s .
• Proprietary synchronous 32 or 64-bit wide DMA_OUT bus used for data streaming from external memory. The bus width is dependant on NPI bus width. This port can stream data in single beat transfers – word (32-bits), double word (64-bit), 16, 32 and 64-word (64-bit only) per one transaction. Maximal sustainable bandwidth at 100MHz NPI_Clk is approx. 300MB/s at 32-bits and 600MB/s at 64-bits.

XPS_NPI_DMA Core Design Parameters

XPS_NPI_DMA I/O Signal Descriptions

Writing and reading to/from DMA_IN and DMA_OUT ports

The point to point unidirectional buses use simple handshaking protocol.

• When (slave) “ready” signal is high the port is open for writing.
• A write is performed when “valid” signal goes high.
• The “data” should be valid when valid signal is high.
• If “valid” signal goes high and the ready is low then the data are discarded (FIFO_IN only).
• The signals are updated on rising edge of clock. 

XPS_NPI_DMA Core Registers

XPS_NPI_DMA has a full access of a microprocessor to the core functionality through a 9 user 32-bit and 7 IPIF Interrupt registers attached to PLBv4.6 bus.

Details of XPS_NPI_DMA Core Regi sters

The parts of the registers (or the whole registers) with a non-capital designation (e.g. wr_fifo_rst) are usually the names of the HDL signals connected to the described register.

Control Register (CR)

The Control Register is used to control basic peripheral functions. All the bit flags are assembled here.

Write Start Address Register (WSA)

Here, the user inputs start address for writing transfer. It is an external memory address for the first byte to be written.

Write Bytes Register (WBR)

Here, the user inputs the number of bytes to written to memory. It is not necessary to align the number of bytes to block size, since the remaining bytes will be padded. If the user sets wr_loop to 1 then the WSA+WBR is the maximal address before the address counter jumps to WSA and starts counting again.

Read Start Address Register (RSA)

Here, the user inputs start address for reading transfer. It is an external memory address for the first byte to be read.

Read Bytes Register (RBR)

Here, the user inputs the number of bytes to be read from the memory. It is not necessary to align the number of bytes to block size, since the remaining bytes will remain in the RdFIFO. If the user sets rd_loop to 1 then the when the byte counter reaches RBR values jumps to 0 (RSA address) and starts counting again.

Read Jumps Register (RJR)

This register is used to input two16bit values to define the reading jumping startegy/algorithm. The read_jump is an address increment between two consecutive reads. If the user want linear read then this is a number of bytes per read block (4 or 8 for single beat xfer). When rotating (transposing) an image this should equal to number of bytes in a row. The parameter rows define how many reads should be done before returning to starting position+block size.

Status Register (SR)

In the status register the peripheral reports of the current status.

Write Address Counter Register (WCR)

Reading this register returns current WRITE address counter value. It can be used to monitor write transfer progress.

Read Address Counter Register (RCR)

Reading this register returns current READ address counter value. It can be used to monitor read transfer progress.

Interrupt registers

With INTR_IPIER register the user can enable/disable peripheral interrupt sources. With INTR_IPISR the user can identify interrupt source. Writing a value to INTR_IPISR also clears interrupt.

Writing 0x7 to INTR_DIER will enable IP interrupt sources and writing 0x80000000 to INTR_DGIER will enable global interrupt.

The image below presents a conection of user logic interrupt to INTR_IPIER and INTR_IPISR.

Programmin model

Write block size	wr_block_size	C_NPI_DATA_WIDTH	type of transfer	Implemented
4 bytes	X”0”	32	1 word xfer
8 bytes	X”0”	64	2 words xfer
16 bytes	X”1”	32-64	4-word cache-line burst
32 bytes	X”2”	32-64	8-word cache-line burst
64 bytes	X”3”	32-64	16-word burst
128 bytes	X”4”	32-64	32-word burst
256 bytes	X”5”	64	64-word burst

Write block size available

Read block size	rd_block_size	C_NPI_DATA_WIDTH	type of transfer	Implemented
4 bytes	X”0”	32	1 word xfer
8 bytes	X”0”	64	2 words xfer
16 bytes	X”1”	32-64	4-word cache-line burst	, not tested
32 bytes	X”2”	32-64	8-word cache-line burst	, not tested
64 bytes	X”3”	32-64	16-word burst
128 bytes	X”4”	32-64	32-word burst
256 bytes	X”5”	64	64-word burst

Read block size available

Example 1

Example of single write transfer from address 0x1C000000 to 0x1C00FFFF using 32-word burst

1. Write 0x1C000000 to WSA

2. Write 0x00010000 to WBR

3. Write 0x00000440 to CR

4. Poll SR until write_xfer_done = 1

Example 2

Example of single linear read transfer from address 0x1C000000 to 0x1C00FFFF using 32-word burst transaction

1. Write 0x1C000000 to RSA

2. Write 0x00010000 to RBR

3. Write 0x00004080 to CR

4. Poll SR until read_xfer_done = 1

Example 3

Example of single transpose read transfer from address 0x1C000000 at image size 750 bytes/row x 480 rows.

1. Write 0x1C000000 to RSA

2. Write 0x00057E40 to RBR

3. Write 0x02EE01DF to RJR (Note 1DF=rows-1)

4. Write 0x00010080 to CR

5. Poll SR until read_xfer_done = 1

In this case the user gets on output port 4 (at C_NPI_DATA_WIDTH = 32) or 8 (at C_NPI_DATA_WIDTH = 64) bytes per every data valid. Further demultiplexing (downto single pixel size if needed) can be done using a FIFO array (for example OUTPUT_DMA_FIFOS).

For using the software driver read function comments in:

#projec t#(or IP repository)\drivers\xps_npi_dma_v1_00_a\src\xps_npi_dma.c

Example 4 (if Reference Design is used): test XPS_NPI_DMA and XPS_FX2 using MB Commands 

XPS_NPI_DMA and XPS_FX2 custom IP blocks are both necessary to connect  (throgh USB connection) host computer's software  and TE USB FX2 module's DRAM.

The MB Commands FX22MB_REG0_START_RX, FX22MB_REG0_START_TX, FX22MB_REG0_STOP are used for data throughput and integrity test.

MB Commands require the XPS_I2C_SLAVE custom IP block and a proper FX2 interrupt handler (i2c_slave_int_handler() function in interrupt.c running on MicroBlaze); the FX2 interrupt handler is called to handle the signal interrupt xps_i2c_slave_0_IP2INTC_Irpt. The i2c_slave_int_handler() function actually execute the I2C delivered MB Command.