Page History
Type | File Prefix | File Extention | Example | Description |
---|---|---|---|---|
Application Note(s) | AN- | |||
Assembly Diagram | AD- | AD-TE0715-02.pdf | Assembly Diagrams with board dimension and connector position as pdf | |
Bill of Materials | BOM- | .csv, .pdf, .xlsx, .ods | ||
Cooler-STEP | STEPSTP- | .zip (.step),.pdf | STEPSTP-26923-TE0715-Heatsink.zip,26923-TE0715-Heatsink.pdf | Cooler 3D STEP (ISO 10303) model (.step) compressed as ZIP-file or pdf document |
EDA library (file(s)) | --- | .LIB-xxx.zip (.lib) | TE0720 GigaZee JBx.LIB-Altium.zip | Altium/Eagle Library Files (.lib) compressed as ZIP-file |
EDA project (file(s)) | --- | .PRJ-xxx.zip | TE0xxx-xx.PRJ-Altium.zip | Altium/Eagle Project Files |
EU declaration of conformity | DoC- | |||
Gerber Files | GB- | .zip | Manufacturing files (Gerber files and numerical control drill files) compressed as ZIP-file | |
Operating Instructions | OI- | |||
Product Brief | PB- | |||
PCB-STEP | STEPSTP- | .zip (.step) | STEPSTP-TE0715-02.zip | PCB 3D STEP (ISO 10303) model compressed as ZIP-file |
PCN | PCN- | PCN-20160114 TE0720-02 to TE0720-03, CPLD upgrade to REV05-v1-20160122_0830.pdf | Product change notifications | |
Pick and Place | PP- | |||
Schematics | SCH- | SCH-TE0726-02M.PDF | PCB Schematic as pdf | |
System Controller | --- | .JED | SC0720_04_1AF.JED | Firmware for PCB-CPLDs (Lattice FPGA). Free Programmer Software available on Lattice Semiconductor. |
Trace Length | TL- | .csv, .pdf, .xlsx, .ods | PCB Trace Length | |
Technical Reference Manual | TRM- | TRM-TE0715-03-v1.0.pdf | ||
Vivado Design | --- | .zip | te0720-test_board-vivado_2016.2-build_03_20160630150948.zip | ZIP files with FPGA Reference Design as TCL script with Batch-Files to create the Vivado project. Design- and Programmer Software available on Xilinx. Attention: Only Programmer (LabTools) is freeware, but depending on FPGA, the Design-Software is not always free. |
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