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Table of Contents |
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The Trenz Electronic TE0701 Carrier Board is a baseboard for 4 x 5 SoMs, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate TE 4 x 5 SoMs.
See page "4 x 5 cm carriers" to get information about the SoMs supported by the TE0701 carrier board.
Refer to http://trenz.org/te0701-info for the current online version of this manual and other available documentation.
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- HDMI connector (1.4 HEAC support), J4
- Micro-USB2 connector, J12
Pmod connector, J5
- Pmod connector, J6
- User push-button ("RESTART" button by default), S2
- User push-button ("RESET" button by default), S1
- 8x red user LEDs, D1 ... D8
- Mini-USB2 connector, J7
- User 4-bit DIP switch, S3
- VITA 57.1 compliant LPC FMC connector, J10
- Barrel jack for 12V power supply, J13
- ARM JTAG connector (DS-5 D-Stream), J15, functionality depends on module
- User 4-bit DIP switch, S4
- Pmod connector, J1
- RJ45 Gigabit Ethernet connector, J14
- SD Card connector, J8
- Pmod connector, J2
- Jumper, J18
- Mini CameraLink connector, J3
- CR1220 Backup-Battery holder, B1
- Trenz Electronic 4 x 5 modules B2B connectors, JB1 ... JB3
- Jumper J16, J17, J21
- Jumper J9, J19, J20
- Analog Devices ADV7511 HDMI Transmitter, U1
- Lattice Semiconductor MachXO2 1200 HC System Controller CPLD, U14
- FTDI FT2232H USB2 to JTAG/UART Bridge, U3
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anchor | Table_OV_CS |
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title | TE0701 Control Signals |
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orientation | portrait |
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repeatTableHeaders | default |
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Control signal | Switch / Button / LED / Pin | Signal Schematic Names | Connected to | Functionality | Notes |
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SC CPLD JTAG Enable | DIP switch S3-3 | JTAGEN | SC CPLD U14, pin 82 | ON: SC CPLD FPGA JTAG enabled, OFF: FPGA SC CPLD JTAG enabled, | - | BOOT MODE | SC CPLD U14, pin 27 | MODE | B2B JB1, pin 31 | Boot Mode for attached module (Flash or SD) | - | Module Reset | SC CPLD U14, pin 13 | RESIN | B2B JB2, pin 17 | Module Reset | - | Global Reset input | Push Button S2 | S2 | SC CPLD U14, pin 2 | Manual reset from user | - | SD Card detection | SD Slot J8, pin 10 | SD_DETECT | SC CPLD U14, pin 40 | Detection Signal for inserted SD Card | Boot mode is set to SD Boot, when SD Card is detected. | Board status indicators | Red LEDs D1 ... D8 | ULED1 ... ULED8 | SC CPLD U14, pins 78, 77, 76, 16, 69, 68, 65, 64 | indicating various board and module status / configuration | Refer to the firmware documentation of the SC CPLD U14 and to the subsection 'LEDs' in section 'On-board Peripherals' for more details and current functionality. | Board 3.3V power indicator | Green LED D22 | 3V3IN | B2B JB1, pin 14, 16 | ON: 3.3V on-board voltage available | - | FMC_VADJ voltage selection | DIP switches S4-1, S4-2, S4-3 | VID0 ... VID2 | SC CPLD U14, pins 34, 35, 38 | sets adjustable voltage for FMC connector | - | I²C control / FMC_VADJ voltage selection | DIP switches S3-2, S3-1 | CM0, CM1 | SC CPLD U14, pins 99, 1 | enabling / disabling I²C control of board functionalities, sets FMC_VADJ voltage (only 3 steps), available to user if FMC_VADJ set by DIP-switch S4 | Refer to the firmware documentation of the SC CPLD U14 and and to the subsection 'DIP switches' in section 'On-board Peripherals' for current functionality and more details. |
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Page properties |
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Notes: - For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
- For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
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FMC LPC Connector
I/O signals and interfaces connected to the FPGA SoCs I/O bank and FMC connector J10:
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anchor | Table_SIP_FMC |
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title | FMC connector J10 interface |
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FMC Connector J2 Pins and Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCIO voltage | Notes |
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I/O | 34 | 17 | B2B JB1 connector | FMC_VADJ / 3V3_FMC | pins usable as single ended I/O's and LVDS pairs | 34 | 17 | B2B JB2 connector | FMC_VADJ / 3V3_FMC | I²C | 2 | - | SC CPLD U14, pin 8, 10 | - | FMC I²C Geographical Address pins GA0 and GA1 set to GND. | JTAG | 4 | - | SC CPLD U14, pin 4, 7, 9, 12 | 3.3V | - | Clock Input | - | 2 | B2B JB1 connector | - | 2x bidirectional reference clock inputs | Control Signals | 2 | - | SC CPLD U14, pin 20, 28 | - | 'PG_C2M', 'FMC_PRSNT' | Reference voltage (FMC_VREF) | 1 | - | B2B JB1 connector, pin 85, 97 B2B JB2 connector, pin 37, 93 | - | FMC sets thresholds of attached module's reference voltage (VREF pins). |
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Channel A of the FTDI chip is configured as JTAG interface (MPSSE) connected to the SC CPLD U14, the JTAG signals are forwarded to the JTAG interface of the attached module if DIP switch S3-3 is in OFFON-position.
Channel B can be used as UART interface routed to the SC CPLD U14 and is available for other user-specific purposes.
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anchor | Table_OBP_PB |
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title | On-board Push Buttons |
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orientation | portrait |
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repeatTableHeaders | default |
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Button | Connected to | Function | Notes |
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S1 | SC CPLD U14, pin 3 | User button, function depends on SC CPLD firmware. | - | S2 | SC CPLD U14, pin 2 | Global Reset of board and attached module, as all power supplies will be switched off on button push and back on again on button release. | - | - |
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Note: Functionality depends also on CPLD Firmware: TE0701 CPLD
On-board LEDs
The TE0701 board is equipped with several LEDs to indicate states and activities.
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There are two baseboard supply voltages VIOTA and VIOTB connected to the 4 x 5 SoM's PL IO-bank. The supply-voltages have following pin assignments on B2B-connectors:
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anchor | Table_RH_DCH |
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title | Document change history |
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Date | Revision | Authors | Description |
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Page info |
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| modified-date |
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| modified-date |
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dateFormat | yyyy-MM-dd |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| - orrectur JTAGEN description for CPLD/Modul access
| | | | - Corrected USB J9 description
- Typos
- update Button description
- Note for J15
| | Jan 2019 | v.73 | John Hartfiel | - correction temperature range
| | Oct 2018 | v.72 | Ali Naseri | - General TRM revision and updated to new style
| 2018-06-13 | | Ali Naseri | - updated Power-on sequence diagram
| 2018-01-12 | | John Hartfiel | | 2017-11-09 | v.60 | John Hartfiel | - add B2B connector section
| 2017-08-15 | | John Hartfiel | - Add VCCIO Jumper Pin location.
- Updated VADJ description.
| 2017-08-14 | v.58 | John Hartfiel | | 2017-05-25 | v.56 | Jan Kumann | - New physical dimensions drawing of the board.
| 2017-05-16 | | Jan Kumann | - A few overall improvements and corrections, new block diagram.
| 2017-04-11 | | Ali Naseri | | 2017-02-15 | | Ali Naseri | - added warning concerning the use of FTDI tools
| 2017-02-15 | v.40 | Ali Naseri | - added power-on sequence diagram
| 2017-01-19 | | Ali Naseri | - correction of table 3 (switch-positions to adjust FMC_VADJ)
- inserted hint to set and measure the PL IO-bank supply-voltages
| 2017-01-13 | | Ali Naseri | - added section for baseboard supply voltage configuration
| 2016-11-29 | | Ali Naseri | - TRM update due to new revision 06 of
- the carrier board.
| 2016-11-28 | v.4 | | - TRM adjustment to the newest
- revision (05) of TE0701 Carrier Board.
| 2014-02-18 | 0.2 | Sven-Ole Voigt | | 2014-01-05 | 0.1 | Sven-Ole Voigt | |
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