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Table of Contents |
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| Scroll Title |
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| anchor | Table_OV_CS |
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| title | TE0701 Control Signals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Control signal | Switch / Button / LED / Pin | Signal Schematic Names | Connected to | Functionality | Notes |
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| SC CPLD JTAG Enable | DIP switch S3-3 | JTAGEN | SC CPLD U14, pin 82 | ON: SC CPLD FPGA JTAG enabled,
OFF: FPGA SC CPLD JTAG enabled, | - | | BOOT MODE | SC CPLD U14, pin 27 | MODE | B2B JB1, pin 31 | Boot Mode for attached module (Flash or SD) | - | | Module Reset | SC CPLD U14, pin 13 | RESIN | B2B JB2, pin 17 | Module Reset | - | | Global Reset input | Push Button S2 | S2 | SC CPLD U14, pin 2 | Manual reset from user | - | | SD Card detection | SD Slot J8, pin 10 | SD_DETECT | SC CPLD U14, pin 40 | Detection Signal for inserted SD Card | Boot mode is set to SD Boot,
when SD Card is detected. | | Board status indicators | Red LEDs D1 ... D8 | ULED1 ... ULED8 | SC CPLD U14, pins
78, 77, 76, 16, 69, 68, 65, 64 | indicating various board and
module status / configuration | Refer to the firmware documentation of the SC CPLD
U14 and to the subsection 'LEDs' in section 'On-board Peripherals'
for more details and current functionality. | | Board 3.3V power indicator | Green LED D22 | 3V3IN | B2B JB1, pin 14, 16 | ON: 3.3V on-board voltage available | - | | FMC_VADJ voltage selection | DIP switches S4-1, S4-2, S4-3 | VID0 ... VID2 | SC CPLD U14, pins 34, 35, 38 | sets adjustable voltage for FMC connector | - | | I²C control / FMC_VADJ voltage selection | DIP switches S3-2, S3-1 | CM0, CM1 | SC CPLD U14, pins 99, 1 | enabling / disabling I²C control of board functionalities,
sets FMC_VADJ voltage (only 3 steps),
available to user if FMC_VADJ set by DIP-switch S4 | Refer to the firmware documentation of the SC CPLD
U14 and and to the subsection 'DIP switches' in section 'On-board
Peripherals' for current functionality and more details. |
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Channel A of the FTDI chip is configured as JTAG interface (MPSSE) connected to the SC CPLD U14, the JTAG signals are forwarded to the JTAG interface of the attached module if DIP switch S3-3 is in OFFON-position.
Channel B can be used as UART interface routed to the SC CPLD U14 and is available for other user-specific purposes.
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There are two baseboard supply voltages VIOTA and VIOTB connected to the 4 x 5 SoM's PL IO-bank. The supply-voltages have following pin assignments on B2B-connectors:
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| Scroll Title |
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| anchor | Table_RH_DCH |
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| title | Document change history |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Authors | Description |
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| Page info |
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| modified-date |
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| modified-date |
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| dateFormat | yyyy-MM-dd |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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| | Page info |
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| infoType | Modified by |
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| type | Flat |
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| showVersions | false |
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| - orrectur JTAGEN description for CPLD/Modul access
| | | | - Corrected USB J9 description
- Typos
- update Button description
- Note for J15
| | v.73 | John Hartfiel | - correction temperature range
| | v.72 | Ali Naseri | - General TRM revision and updated to new style
| | 2018-06-13 | | Ali Naseri | - updated Power-on sequence diagram
| | 2018-01-12 | | John Hartfiel | | | 2017-11-09 | v.60 | John Hartfiel | - add B2B connector section
| | 2017-08-15 | | John Hartfiel | - Add VCCIO Jumper Pin location.
- Updated VADJ description.
| | 2017-08-14 | v.58 | John Hartfiel | | | 2017-05-25 | v.56 | Jan Kumann | - New physical dimensions drawing of the board.
| | 2017-05-16 | | Jan Kumann | - A few overall improvements and corrections, new block diagram.
| | 2017-04-11 | | Ali Naseri | | | 2017-02-15 | | Ali Naseri | - added warning concerning the use of FTDI tools
| | 2017-02-15 | v.40 | Ali Naseri | - added power-on sequence diagram
| | 2017-01-19 | | Ali Naseri | - correction of table 3 (switch-positions to adjust FMC_VADJ)
- inserted hint to set and measure the PL IO-bank supply-voltages
| | 2017-01-13 | | Ali Naseri | - added section for baseboard supply voltage configuration
| | 2016-11-29 | | Ali Naseri | - TRM update due to new revision 06 of
- the carrier board.
| | 2016-11-28 | v.4 | | - TRM adjustment to the newest
- revision (05) of TE0701 Carrier Board.
| | 2014-02-18 | 0.2 | Sven-Ole Voigt | | | 2014-01-05 | 0.1 | Sven-Ole Voigt | |
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