Page History
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Product Specification
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Port Description
| Name | Direction | Pin | Description |
|---|---|---|---|
| JTAGEN | in | 26 | Switch JTAG between CPLD and FPGA (logical one:CPLD, logical zero: FPGA) |
| M_TMS | IN | 29 | JTAG from B2B connector |
| M_TCK | IN | 30 | JTAG from B2B connector |
| M_TDI | IN | 32 | JTAG from B2B connector |
| M_TDO | OUT | 1 | JTAG from B2B connector |
| C_TMS | OUT | 21 | JTAG to FPGA |
| C_TCK | OUT | 17 | JTAG to FPGA |
| C_TDI | OUT | 23 | JTAG to FPGA |
| C_TDO | IN | 20 | JTAG to FPGA |
| XIO | IN | 4 | FPGA access W22 PIN |
| FPGA_IO | INOUT | 10 | FPGA access U22 PIN |
| RESIN | IN | 16 | RSIN from B2B connector |
| DONE | IN | 28 | FPGA Configuration DONE_0 Pin |
| PROG_B | OUT | 27 | FPGA Configuration PROGRAM_B_0 Pin |
| PGOOD | OUT | 12 | PGOOD to B2B connector |
| PG_SENSE | IN | 25 | 3.3V |
| EN1 | IN | 11 | Power Enable from B2B Connector |
| LED1 | OUT | 8 | Module LED D1 (Green) |
| LED2 | OUT | 9 | Module LED D2 (Red) |
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Functional Description
JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN ( (ogical one:CPLD, logical zero: FPGA).
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Appx. A: Change History and Legal Notices
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Overview
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