Name	Direction	Pin	Description
JTAGEN	in	26	Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA)
M_TMS	IN	29	JTAG from B2B connector
M_TCK	IN	30	JTAG from B2B connector
M_TDI	IN	32	JTAG from B2B connector
M_TDO	OUT	1	JTAG from B2B connector
C_TMS	OUT	21	JTAG to FPGA
C_TCK	OUT	17	JTAG to FPGA
C_TDI	OUT	23	JTAG to FPGA
C_TDO	IN	20	JTAG to FPGA
XIO	IN	4	FPGA access W22 PIN
FPGA_IO	INOUT	10	FPGA access U22 PIN
RESIN	IN	16	RESETIN from B2B connector (Negative Reset)
DONE	IN	28	FPGA Configuration DONE_0 Pin
PROG_B	OUT	27	FPGA Configuration PROGRAM_B_0 Pin
PGOOD	OUT	12	PGOOD to B2B connector
PG_SENSE	IN	25	from module generated 3.3V Voltage
EN1	IN	11	Power Enable from B2B Connector (Positive Enable)
LED1	OUT	8	Module LED D1 (Green)
LED2	OUT	9	Module LED D2 (Red)

FPGA configuration process will be stared, if RESIN, PG_SENSE and EN1 is ONE.

LED	STATUS	Condition	User defined
LED1	ON	RSIN=0	---
LED1	Blink	RSIN=1, DONE=0	---
LED1	X	RSIN=1, DONE=1	FPGA_IO Pin
LED2	ON	RSIN=0	---
LED2	Blink	RSIN=1, DONE=0	---
LED2	X	RSIN=1, DONE=1	XIO Pin

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Appx. A: Change History and Legal Notices

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