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FPGA PinSignal NameSignal Description
N17ETH-RSTEthernet reset, active-low.
N15LINK_LEDEthernet LED pin indication mode: in mode 1 - LINK, in mode 2 - ACT.
R16MDC

Ethernet management clock.

P17MDIOEthernet management data.
P14ETH_TX_D0Ethernet transmit data 0. Output to Ethernet PHY.
P15ETH_TX_D1Ethernet transmit data 1. Output to Ethernet PHY.
R14ETH_TX_ENEthernet transmit enable.
N13ETH_RX_D0Ethernet receive data 0. Input from Ethernet PHY. 
N14ETH_RX_D1Ethernet receive data 0. Input from Ethernet PHY. 
P20ETH_RX_DVEthernet receive data valid.

All signals are connected to the FPGA bank 14 and correspond to LVCMOS33 standard.

MAC Address

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EEPROM

TE0712-02 module has a 2 Kbit Serial Electrically Erasable PROM (SEEPROMEEPROM, U7).  It provides pre-programmed 48-bit Extended Unique Identifier (EUI-48™) to identify network hardware MAC address which is write-protected to ensure tamper-proof designs. This SEEPROM can be accessed by UNI/O® serial interface bus using Manchester encoding techniques. The clock and data are combined into a single, serial bit stream (SCIO), where the clock signal is extracted by the receiver to correctly decode the timing and value of each bit. The bus is controlled by a master device (Xilinx Artix-7) which determines the clock period, controls the bus access and initiates all operations, while the SEEPROM works as a slave. Refer to Microchip's 11AA02E48 datasheet for more information.

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