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I/O signals connected to the FPGA's I/O banks and B2B connector:

Bank	Type	B2B Connector	I/O Signal Count	Voltage	Notes
0	HR	-	-	3.3V	Configuration bank
12	HR	JM2	50 I/O-pins 24 LVDS-pairs possible	User	HR-Banks support voltages from 1.2V to 3.3V standards. NOTE: BANK 12 IS NOT AVAILABLE ON THE K70T DEVICE.
13	HR	JM1	48 I/O-pins 24 LVDS-pairs possible	User	HR-Banks support voltages from 1.2V to 3.3V standards.
14	HR	JM1, JM3	8 I/O-pins, 4 I/O-pins (2 LVDS-pairs possible)	3.3V	pins at B2B connector JM1, 3.3V IO-voltage.
15	HR	JM2	18 I/O-pins 9 LVDS-pairs possible	User	HR-Banks support voltages from 1.2V to 3.3V standards.
16	HR	JM1	16 I/O-pins 8 LVDS-pairs possible	User	HR-Banks support voltages from 1.2V to 3.3V standards.
32	HP	NC	-	-	Bank not used.
33	HP	NC	-	-	Bank not used.
34	HP	NC	-	-	Bank not used.

Table 2: Voltage ranges and pin-outs of available logic banks of the FPGA.

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin Name	Mode	Function	Default Configuration	B2B Connector
PGOOD	Output	Power Good	Active high when all on-module power supplies are working properly.	JM1-30
RESIN	Input	Reset	Active low reset signal, drive low to keep the system in reset (FPGA pin PROG_B will be driven by CPLD).	JM2-18
JTAGMODE	Input	JTAG Select	Low for normal operation, high (3.3V) to programm the System Controller CPLD.	JM1-89

Table 4: Pin-description of System Controller CPLD

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There are four LED's available on TE0741 SoM. Two status LED's (D3 and D4) and two user configurable LED's (D1 and D2).

LED	Color	Connected to	Description and Notes
D1	green	LED2	User configurable LED.
D2	red	LED1	User configurable LED.
D3	green	DONE	Reflects inverted DONE signal, ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the the 3.3V power rail is not available. After FPGA configuration the user can use USRACCESSE2 to control Done LED.
D4	green	C_LED	Connected to the system controller indicating status of the module: Steadily lit: RESIN pin is kept low. Blinking fast (0.1s on/off): Power sequencing fault (PG_ALL = 0). Blinking at medium speed (0.5s on/off): Power sequencing has completed but the FPGA is not configured (PG_ALL = 1, DONE = 0). Blinking slow (1s on/off): FPGA is configured and board is ready (PG_ALL = 1, DONE = 1). It is also possible to program the System Controller CPLD to connect this LED to FPGA pin named XIO.

Table 5: Description of the on board LED's.

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Variants Currently In Production

Table 11: Differences between variants of Module TE0741.

Parameter	Min	Max	Units	Notes
VIN supply voltage	-0.3	6.5	V	-
3.3VIN supply voltage	-0.1	3.6	V	-
PL IO bank supply voltage for HR I/O Banks (VCCO)	-0.5	3.6	V	-
I/O input voltage for HR I/O banks	-0.4	VCCO_X+0.55	V	-
GT receiver (RXP/RXN) and transmitter (TXP/TXN)	-0.5	1.26	V	Xilinx datasheet DS182
Voltage on module JTAG pins	-0.5	VCCO_0+0.45	V	VCCO_0 is 3.3V nominal.
Storage temperature	-55	+125	°C	-

Table 12: Absolute maximum ratings.

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Parameter	Min	Max	Units	Notes	Reference Document
VIN supply voltage	2.4	5.5	V	-	EP53F8QI data sheet
3.3VIN supply voltage	3.135	3.465	V	3,3V ± 5%	-
PL I/O bank supply voltage for HR I/O banks (VCCO)	1.14	3.465	V	-	Xilinx datasheet DS182
I/O input voltage for HR I/O Banks	- 0.20	VCCO+0.2	V	-	Xilinx datasheet DS182
GT receiver (RXP/RXN) and transmitter (TXP/TXN)	(*)	(*)	-	-	Xilinx datasheet DS182
Voltage on Module JTAG pins	3.135	3.

6

465

V

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MachX02 Family datasheet

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Table 13: Recommended operation conditions.

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Date	Revision	Notes	PCN	Documentation link
	01	First production release
	02	improved power-sequencing added differential terminator to bank 14 clock input

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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