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changes.mady.by.user Ali Naseri

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I/O signals connected to the FPGA's I/O banks and B2B connector:

BankTypeB2B ConnectorI/O Signal CountVoltageNotes

0

HR

-

-

3.3VConfiguration bank

12

HR

JM2

50 I/O-pins

24 LVDS-pairs possible

User

HR-Banks support voltages from 1.2V to 3.3V standards.

NOTE: BANK 12 IS NOT AVAILABLE ON THE K70T DEVICE.

13

HR

JM1

48 I/O-pins

24 LVDS-pairs possible

User

HR-Banks support voltages from 1.2V to 3.3V standards.

14

HR

JM1,

JM3

8 I/O-pins,

4 I/O-pins (2 LVDS-pairs possible)

3.3V

pins at B2B connector JM1, 3.3V IO-voltage.

15

HR

JM2

18 I/O-pins

9 LVDS-pairs possible

User

HR-Banks support voltages from 1.2V to 3.3V standards.

16

HR

JM1

16 I/O-pins

8 LVDS-pairs possible

User

HR-Banks support voltages from 1.2V to 3.3V standards.

32

HP

NC

-

-

Bank not used.

33

HP

NC

-

-

Bank not used.
34HPNC--Bank not used.

Table 2:  Voltage ranges and pin-outs of available logic banks of the FPGA.

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault ConfigurationB2B Connector
PGOODOutputPower GoodActive high when all on-module power supplies are working properly.JM1-30
RESINInputResetActive low reset signal, drive low to keep the system in reset (FPGA pin PROG_B will be driven by CPLD).JM2-18
JTAGMODEInputJTAG SelectLow for normal operation, high (3.3V) to programm the System Controller CPLD.JM1-89

Table 4: Pin-description of System Controller CPLD

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There are four LED's available on TE0741 SoM. Two status LED's (D3 and D4) and two user configurable LED's (D1 and D2).

LEDColorConnected toDescription and Notes
D1greenLED2User configurable LED.
D2redLED1User configurable LED.
D3greenDONE

Reflects inverted DONE signal, ON when FPGA is not configured, OFF as soon as PL is configured.

This LED will not operate if the the 3.3V power rail is not available.

After FPGA configuration the user can use USRACCESSE2 to control Done LED.

D4greenC_LED

Connected to the system controller indicating status of the module:

Steadily lit: RESIN pin is kept low.

Blinking fast (0.1s on/off): Power sequencing fault (PG_ALL = 0).

Blinking at medium speed (0.5s on/off): Power sequencing has completed but the FPGA is not configured (PG_ALL = 1, DONE = 0).

Blinking slow (1s on/off): FPGA is configured and board is ready (PG_ALL = 1, DONE = 1).

It is also possible to program the System Controller CPLD to connect this LED to FPGA pin named XIO.

Table 5: Description of the on board LED's.

Note: if FPGA logic toggles DONE pin (to control D3) then D4 will toggle at random, as changing value on DONE will change the blink frequency of D4.

Note

DONE LED will be ON as long as FPGA is NOT configured and will be OFF when FPGA is configured successfully. If user STARTUPE2 primitive is used in user design then DONE LED is controlled by the user design and can be on/off/blink or have any other functionality defined by the user.

Clocking

To enable the PLL (phase-locked loop) clock generator Si5338A (U2), CLK_EN-signal (bank 14, pin C26) must be set to high, to activate the 25 MHz reference clock SiT8208AI (U3). The GTX reference clocks 0 and 2 have to be provided by the user on B2B connector JM3.

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Designator /

Module Variant

U1

U15
TE0741-02-070-2CFXC7K70T-2FBG676C-
TE0741-02-160-2CFXC7K160T-2FBG676C-
TE0741-02-325-2CFXC7K325T-2FBG676CEN63A0QI
TE0741-02-410-2CFXC7K325T-2FBG676CEN63A0QI
TE0741-02-070-2IFXC7K70T-2FBG676I-
TE0741-02-160-2IFXC7K160T-2FBG676I-
TE0741-02-325-2IFXC7K325T-2FBG676IEN63A0QI
TE0741-02-160-2C1XC7K160T-2FFG676C-

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Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsNotes

VIN supply voltage

-0.36.5V-
3.3VIN supply voltage

-0.1

3.6 V-
PL IO bank supply voltage for HR I/O Banks (VCCO) -0.53.6 V-
I/O input voltage for HR I/O banks-0.4 VCCO_X+0.55 V-
GT receiver (RXP/RXN) and transmitter (TXP/TXN)-0.51.26 VXilinx datasheet DS182
 Voltage on module JTAG pins

-0.5

 VCCO_0+0.45 VVCCO_0 is 3.3V nominal.
Storage temperature

-55

+125

 °C-

Table 12: Absolute maximum ratings.

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Recommended Operation Conditions

ParameterMinMaxUnitsNotesReference Document
VIN supply voltage2.45.5 V-EP53F8QI data sheet 
3.3VIN supply voltage3.1353.465 V

3,3V ± 5%

 -
PL I/O bank supply voltage for HR

I/O banks (VCCO)

1.143.465 V-Xilinx datasheet DS182
I/O input voltage for HR I/O Banks- 0.20VCCO+0.2 V-Xilinx datasheet DS182
GT receiver (RXP/RXN) and transmitter (TXP/TXN)(*)(*)--
Xilinx datasheet
* check datasheet DS182
Voltage on Module JTAG pins3.135 3.465 V--

Table 13: Recommended operation conditions.

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Hardware Revision History

DateRevisionNotesPCNDocumentation link
 01First production release  
 02
  • improved power-on -sequencing
  • added differential terminator
    to bank 14 clock input 
  

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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Review
DateRevisionContributorsDescription
2016-12-142016-12-06

 

 

Ali Naseri

TRM revision

2013-12-020.1

 

 
initial version

Disclaimer

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