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Overview
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Table of Contents
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Overview
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Online version of this manual and other related documents can be found at https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TE0711
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All this on a tiny footprint, smaller than a credit card, at
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the most competitive price.
Block Diagram
Figure 1: TE0711-01 Block Diagram
Main Components
Figure 2: TE0711 (REV 01).
- Artix-7 (15T to 100T) FPGA
- EN6347QI voltage Regulator 1.0V
- EN5311QI voltage Regulator 1.8V
- S25FL256S 32 Mbyte Quad SPI Flash memory
- Dual USB to UART/FIFO Bridge (FT2232H)
- TPS27082L load switch for 3.3V voltage level
- B2B connector JM1 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- B2B connector JM2 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- B2B connector JM3 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- System Controller CPLD (Lattice LCMXO2-256HC): 256 Macrocell CPLD
- SiT8008AI 100 MHz reference clock (connected to FPGA bank 14)
- SiT8008AI 12 MHz reference clock (connected to USB to UART/FIFO Bridge)
- EEPROM (configuration data for USB to UART/FIFO Bridge)
- TPS3805H33 voltage detector for generating "Power OK"-signal indicating successful power-on-sequencing
Key Features
Industrial-grade Xilinx Artix-7
XC7A15T - XC7A100T (Rick Martin added range of FPGA)(15T to 100T) SoM (System on Module), supported by the free Xilinx Vivado WebPACK tool
Rugged for shock and high vibration
- FTDI FT2232HQ USB 2.0 High Speed to UART/FIFO
32
MbyteMByte QSPI Flash memory (with XiP support)
100 MHz MEMS oscillator
Plug-on module with
2×2 × 100-pin and
1×1 × 60-pin high-speed hermaphroditic strips
178 FPGA I/Os (84 differential pairs)
andare available
on boardon board-to-board connectors
On-board high-efficiency DC-DC converters
4.0 A x 1.0 V power rail
1.0 A x 1.8 V power rail
1.0 A x 1.5 V power rail
System management and power sequencing
eFUSE bit-stream encryption
AES bit-stream encryption
- 3 user LEDs
- FTDI FT2232H USB2 High Speed IC Chip
User LED
Evenly-spread supply pins for good signal integrity
Assembly options for cost or performance optimization available upon request.
...
Main Components
| Top View | Bottom View |
Artix-7 FPGA
32 Mbyte Quad SPI Flash memory
Dual USB to UART/FIFO Bridge (FT2232H)
System Controller CPLD
Oscillator 100MHz - System clock for FPGA
- EEPROM - for FT2232H
Oscillator 12MHz - for FT2232H
Detailed Description
PL Programmable Logic
TE0711 SoM is based on the Artix-7 Series Families FPGA and is available in five different logic densities (A15T,A35T,A50T,A75T,A100T).
The devices can be programmed with the free Xilinx Vivado WebPACK software. Further information on the Artix-7 FPGA can be found in the Xilinx document 7 Series FPGAs Overview (DS180).
| Board | FPGA | Logic Cells | Flip-Flops | BRAM |
|---|---|---|---|---|
| TE0711-01-15 | XC7A15T | 16,640 | 20,800 | 25 |
| TE0711-01-35 | XC7A35T | 33,280 | 41,600 | 50 |
| TE0711-01-50 | XC7A50T | 52,160 | 65,200 | 75 |
| TE0711-01-75 | XC7A75T | 75,520 | 94,400 | 105 |
| TE0711-01-100 | XC7A100T | 101,440 | 126,800 | 135 |
Configuration Modes
| Mode | Interface | Notes |
|---|---|---|
| JTAG | JTAG | For debugging purposes |
| SPI Flash | SPI Master 4-bit mode | Main configuration mode. SPI Flash is used to store FPGA bitstream(s), PS Executable Object code and user data. |
TE0711 Configuration Modes
| Config Pin | Setting | Notes |
|---|---|---|
| M0 | 3.3V | Bootmode setting: Master SPI |
| M1 | 0V | |
| M2 | 0V | |
| CFGBVS | 3.3V | Select 3.3V as Config Bank I/O Voltage |
| PUDC | Strong pull-up to 3.3V | Pre-configuration pull-ups are DISABLED |
TE0711 Configuration pin settings
Configuration Memory
TE0711 standard assembly option includes 32MByte SPI Flash for configuration and data storage. This memory is large enough to hold at least 4 uncompressed FPGA Bitstreams.
| Parameter | Value | Notes |
|---|---|---|
| Memory size (MBytes) | 32 | |
| Vendor | spansion | http://www.spansion.com |
| Device type | S25FL256SAGBHI20 | |
| Vivado CFGMEM | s25fl256sxxxxxx0-spi-x1_x2_x4 | Value to be used with Vivado labtools flash programmer |
| Vivado Board Part File Interface name | SPI Flash |
Parameter values for the SPI Flash memory included in the standard assembly option.
XADC
XADC is configured with internal reference voltage option. All XADC inputs that are shared with FPGA I/O are available in the B2B Connector. There is no access to the dedicated XADC input pins.
PS Processing System
TE0711 has no hard PS subsystem. Microblaze Soft Processor or Microblaze MCS can be used, they are both free of charge and included with Xilinx free Vivado Webpack version.
| Processor | Bus Interfaces | Peripherals |
|---|---|---|
| Microblaze MCS | Custom | UART, GPIO, Timer |
| Microblaze | AXI4, AXI4-Stream, LMB | Vivado IP Catalog |
Processing System Program Memory content can be embedded in the bitstream or loaded from SPI Flash by a bootloader.
Microblaze™
Microblaze MCS
Example Microblaze MCS system, reset, clock, UART and LEDS to GPIO are connected by Vivado Board Part Interface wizard, no constraint files used or needed. This example Processing System uses less than 5% of A35T logic resources.
Clock Sources
| IC Designator | Description | Frequency | Used as | FPGA Pin | IO Standard | Vivado Board Part Interface |
|---|---|---|---|---|---|---|
| U3 | MEMS Oscillator | 12MHz | Clock for FT2232H | n/a | n/a | not available (no connection to FPGA) |
| U8 | MEMS Oscillator | 100MHz | System Clock | P17 | LVCMOS33 | System Clock |
In standard assembly option MEMS oscillator with 100MHz Frequency and 50 ppm stability is used. Other frequencies possible for custom order.
Reset Sources
| Reset Type | Source | Notes |
|---|---|---|
| Power On Reset | System Controller | PROG_B released after power on causing FPGA reconfiguration |
| B2B Reset | JM2.18 | Active low value forces FPGA reconfiguration |
| Dummy Reset | FPGA pin D9 | Can be used as reset with fixed always inactive value if needed (may have to add pullup or pulldown constraint) |
| Soft Reset | Any FPGA B2B I/O | User defined soft reset input with user defined polarity |
| Debug Reset | Microblaze MDM | JTAG debugger soft reset |
LEDS
There are 3 LED's directly connected to FPGA I/O Pins. Vivado Board Part Interface (GPIO) name: "LEDS".
LED | Color | IOSTANDARD | FPGA Pin | Vivado Board Part name | GPIO Index" | Description |
|---|---|---|---|---|---|---|
| D1 | red | LVCMOS18 | A8 | "Module LEDS" : sys_led | 0 | User LED |
| D2 | green | LVCMOS33 | R17 | "Module LEDS" : led2 | 1 | User LED |
| D3 | green | LVCMOS33 | L15 | "Module LEDS" : led3 | 2 | User LED, active low |
Dual channel USB UART/FIFO
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Initial Delivery State
| Storage device name | Content | Notes |
|---|---|---|
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
EFUSE USER | Not programmed | - |
EFUSE Security | Not programmed | - |
Table 1: Initial delivery state
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
I/O signals connected to the FPGA's I/O banks and B2B connector:
| Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
|---|---|---|---|---|---|
0 | HR | - | - | 3.3V | Configuration bank |
14 | HR | JM1, JM2 | 8 I/O-pins, 18 I/O-pins (9 LVDS-pairs possible) | 3.3V | HR-Banks support voltages from 1.2V to 3.3V standards. See the Artix-7 datasheet (DS181) for the allowable voltage range. |
15 | HR | JM1 | 48 I/O-pins 24 LVDS-pairs possible | user | as above |
16 | HR | JM1 | 6 I/O-pins 3 LVDS-pairs possible | 1.8V | as above |
| 34 | HR | JM1, JM3 | 48 I/O-pins 24 LVDS-pairs possible | user | as above |
| 35 | HR | JM2 | 50 I/O-pins 24 LVDS-pairs possible | user | as above |
Table 2: Voltage ranges and pin-outs of available logic banks of the FPGA
Please use Master Pinout Table table as primary reference for the pin mapping information.
JTAG Interface
JTAG access to the Xilinx Artix-7 and to the System Controller CPLD is provided through B2B connector JM2.
| JTAG Signal | B2B Connector |
|---|---|
| TCK | JM2-99 |
| TDI | JM2-95 |
| TDO | JM2-97 |
| TMS | JM2-93 |
| JTAGSEL | JM1-89 |
Table 3: Pin-mapping of JTAG Interface on B2B connector
| Note |
|---|
Select by JTAGSEL pin on B2B connector JM1-89 either to access FPGA Artix-7 (JTAGSEL pin driven low or open) or System Controller via JTAG (JTAGSEL pin driven high). The use of Xilinx legacy development tools (ISE, Impact) is not recommended. Impact recognizes only A100T, any smaller Artix-7 FPGA is not recognized as Xilinx FPGA by Impact. |
System Controller I/O Pins
Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
| Pin Name | Mode | Function | Default Configuration | B2B Connector |
|---|---|---|---|---|
| STAT_SC2 | Output | Power Good | Active high when all on-module power supplies are working properly. | JM1-30 |
| NRST_SC0 | Input | Reset | Active low reset signal, drive low to keep the system in reset (FPGA pin PROG_B will be driven by CPLD) | JM2-18 |
| JTAGSEL | Input | JTAG Select | Low for normal operation, high (3.3V) to programm the System Controller CPLD | JM1-89 |
| EN_SC3 | Input | Enable FPGA Core Voltage supply | High (3.3V) or open for normal operation, low to stop power-on sequencing | JM1-28 |
Table 4: Pin-description of System Controller CPLD
LEDs
On the SoM TE0710 there is a total of 3 LEDS available. Two LEDs are status LEDs, one can freely used in costumer designs. The user LED is routed to the FPGA by the net with the schematic-name 'USERLED'.
When the FPGA is not configured the status LEDs will flash continuously. Finally once FPGA configuration has completed the status LEDs can be used in the user's FPGA design.
| LED | Color | Connected to pin | Description and Notes |
|---|---|---|---|
| D1 | red | SYSLED2 | User LED, active HIGH, connected to FPGA Pin A8 |
| D2 | green | SYSLED4 | User LED, active HIGH, connected to FPGA Pin R17 |
| D3 | green | SYSLED3 | User LED, active LOW, connected to FPGA Pin L15 |
| D4 | green | SYSLED1 | System Controller status LED, connected to CPLD |
Table 5: Description of the on board LEDs
Clocking
The TE0710 is equipped with two Sitara reference clocks to provide clock signals to the Ethernet PHYs and for the on board 512 MByte DDR3 SRRAM.
| Clock | Frequency | IC | Connected to | Notes |
|---|---|---|---|---|
Reference oscillator clock for USB to UART/FIFO Bridge (FT2232H) | 12 MHz | U9 SiT8008AI-73-XXS-12.000000E | IC U6, FTDI FT2232H | - |
| FPGA bank 14 reference clock input | 100 MHz | U8 SiT8008AI-73-XXS-100.000000E | FPGA bank 14, pin P17 | reference clock for general user purposes |
Table 6: Clocks overview
Onboard Peripherals
32 Mbyte Quad SPI Flash Memory
An SPI flash memory S25FL256S (U7) is provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data rate will be dependent on the bus width and clock frequency.
| Note |
|---|
SPI Flash QE (Quad Enable) bit must be set, or the FPGA would not configure from Flash. This bit is always set at manufacturing. |
System Controller
The system controller is used to coordinate the configuration of the FPGA. The FPGA is held in reset (by driving the PROG_B signal) until the power supplies have sequenced. Low level at NRST_SC0 pin also resets the FPGA. This signal can be driven from the user’s PCB via the B2B connector pin JM2-18. Input EN_SC3 is also gated to FPGA Reset and should be open or pulled up for normal operation. EN_SC3 low turns off on board DCDC converters and stops power-on sequencing.
It is possible for the user to create their own system controller design using the Lattice Diamond software. Once created the design can be programmed into the device using the JTAG pins. The signal JTAGSEL should be set to 3.3V to enable programming mode. For normal operation it should be set to 0V.
There are one status LED connected to the system controller CPLD. When the FPGA is not configured the LED will flash continuously. Finally once FPGA configuration has completed the LEDs can be used in the user's FPGA design.
Dual channel USB to UART/FIFO
The TE0711-01 SoM has on-board USB 2.0 High Speed to UART/FIFO IC FT2232HQ from FTDI. Channel A can only be used in simple UART mode, Channel B can be used as UART, in
...
FT245 FIFO mode, JTAG (MPSSE) or High Speed Serial modes
...
.
All FT2232HQ-pins are connected to bank 14 with fixed 3.3V VCCIO and should be used with LVCMOS33 I/O Standard.
There is also a standard 256 Byte EEPROM connected to the FT2232HQ-chip available to store custom
...
configuration settings
...
. EEPROM settings can be changed using FTDI provided tools that can be downloaded from FTDI website. See FTDI website for more information.
...
Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 2A for system startup is recommended.
| Power Input Pin | Voltage Range | Max Current |
|---|---|---|
| VIN | 3.3V to 5.5V | Typical 200mA, depending on customer design and connections. |
| 3.3VIN | 3.3V | Typical 50mA, depending on customer design and connections. |
Table 7: maximal current of power supplies
| Tip |
|---|
Vin and Vin 3.3V can be connected to the same source (3.3 V). |
Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC/DC converter efficiency (it decreases when VIN/VOUT ratio rises).
Power-On Sequence
For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/O's are 3-stated at power-on until System Controller sets STAT_SC2 signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10,12 or 91, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS181 (for Artix7) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0711-01 module.
A 3.3V supply is also needed and must be supplied from the user's PCB. An output 3.3V supply is available on some of the board connector pins (see section 'Power Rails'). The input 3.3VIN will be switched to the internal 3.3V voltage level after the FPGA 1.0V supply is stable. Than 3.3V supply will be available on the B2B connector pins.
The regulators can be powered from the 3.3V supply or a 5V supply if preferred. The options for powering the board are as follows:
- Apply 5V to pins VIN and 3.3V to pins 3.3VIN on the board connector
- Apply 3.3V to pins VIN and 3.3VIN on the board connectors.
Power Rails
Voltages on B2B- Connectors | B2B JM1-Pin | B2B JM2-Pin | Direction | Note |
|---|---|---|---|---|
| VIN | 1, 3, 5 | 2, 4, 6, 8 | input | supply voltage |
| 3.3VIN | 13, 15 | - | input | supply voltage |
| VCCIO15 | 9, 11 | - | input | high range bank voltage |
| VCCIO34 | - | 1, 3 | input | high range bank voltage |
| VCCIO35 | 7, 9 | input | high range bank voltage | |
| 3.3V | 14 | 10, 12, 91 | output | internal 3.3V voltage level |
| 1.8V | 39 | - | output | internal 1.8V voltage level |
Table 8: Power rails of SoM on B2B connectors
Bank Voltages
| Bank | Schematic Name | Voltage | Range |
|---|---|---|---|
| 0 Config | 3.3V | 3.3V | - |
| 14 | 3.3V | 3.3V | - |
| 15 | VCCIO15 | user | HR: 1.2V to 3.3V |
| 16 | 1.8V | 1.8V | - |
| 34 | VCCIO34 | user | HR: 1.2V to 3.3V |
| 35 | VCCIO35 | user | HR: 1.2V to 3.3V |
Table 9: Range of FPGA's bank voltages
See the Artix7 datasheet DS181 for the allowable voltage range.
Board to Board Connectors
| Include Page | ||||
|---|---|---|---|---|
|
Variants Currently In Production
IC Designator / Module Variant | U5 |
|---|---|
| TE0711-01-100-2C | XC7A100T-2CSG324C |
| TE0711-01-35-2C | XC7A35T-2CSG324C |
| TE0711-01-100-2I | XC7A100T-2CSG324I |
| TE0711-01-35-2I | XC7A35T-2CSG324I |
Table 10: Differences between variants of Module TE0711-01
Technical Specifications
Absolute Maximum Ratings
| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
VIN supply voltage | -0.3 | 7.0 | V | EN6347QI / EN5311QI data sheet |
| 3.3VIN supply voltage | -0.1 | 3.6 | V | - |
| PL IO bank supply voltage for HR I/O Banks (VCCO) | -0.5 | 3.6 | V | - |
| I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - |
| Voltage on module JTAG pins | -0.5 | VCCO_0+0.45 | V | VCCO_0 is 3.3V nominal. |
| Storage temperature | -55 | +125 | °C | - |
Table 11: Absolute maximum ratings
Recommended Operation Conditions
| Parameter | Min | Max | Units | Notes | Reference Document |
|---|---|---|---|---|---|
| VIN supply voltage | 2.4 | 5.5 | V | - | EN5311QI data sheet |
| 3.3VIN supply voltage | 3.135 | 3.465 | V | - | 3,3V ± 5% |
| PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | - | Xilinx datasheet DS181 |
| I/O input voltage for HR I/O Banks | - 0.20 | VCCO + 0.2 | V | - | Xilinx datasheet DS181 |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | - | 3,3V ± 5% |
Table 12: Recommended operation conditions
| Note |
|---|
| Please check Xilinx datasheet (DS181) for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
...
Channel A (Vivado Board Part Interface name: "FTDI Channel A")
...
...
FT2232H pin connection to FPGA I/O, all pins are connected to bank B14 with fixed 3.3V VCCIO and should be used with LVCMOS33 I/O Standard.
More information is available from FTDI website:
Board-to-Board Connectors
View and download specifications of connectors used on this module here: Samtec LSHM
View and download the connector pinout for this module in the master pinout table here: Master Pinout Table
Initial Delivery state
| Storage device name | Content | Notes |
|---|---|---|
| FT2232H EEPROM | Empty, not programmed | |
| SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
| SPI Flash Quad Enable bit | Programmed | |
| SPI Flash main array | demo design | |
| EFUSE USER | Not programmed | |
| EFUSE Security | Not programmed |
Revision History For This Product
| Revision | Changes |
|---|---|
| 01 | Current Hardware Revision, no changes |
Technical Specification
Absolute Maximum Ratings
...
Physical Dimensions
- Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
- Mating height with standard connectors: 8mm
- PCB thickness: 1.6mm
- Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
Download physical dimensions diagrams here: TE0711 Physical Dimensions
Power Supplies
| Vin | 3.3 V to 5.5 V | Typical 200mA, depending on customer design and connections |
| Vin 3.3V | 3.3 V | Typical 50mA, depending on customer design and connections |
For startup, a power supply with minimum current capability of 2A is recommended.
| Tip |
|---|
Vin and Vin 3.3V can be connected to the same source (3.3 V). |
| Commercial grade modules | 0 °C to +70 °C |
| Industrial grade modules | -40 °C to +85 °C |
| Note |
|---|
Depending on the customer design, additional cooling might be required. |
Weight
| TBDg | Without bolts |
| TBDg | With bolts screwed to the module |
Downloads For This Product
Recommended Software: Xilinx Vivado WebPACK (free license)
| Note |
|---|
| A15T, A35T, A50T, A75T are not supported by Xilinx legacy tools (ISE, Impact). |
The schematic is available for download here: TE0711 Schematic
Resources
All dimensions are shown in mm.
Figure 3: Physical Dimensions of the TE0711-01 board
Weight
| 20.6 g | Plain module |
| 8.8 g | Set of bolts and nuts |
Revision History
Hardware Revision History
| Date | Revision | Notes | PCN | Documentation link |
|---|---|---|---|---|
| 01 | First production release Current Hardware Revision |
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Document Change History
| Date | Revision | Contributors | Description |
|---|---|---|---|
| 2016-12-20 | Ali Naseri | TRM revision | |
| 2015-06-05 | 0.1 | initial version |
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Disclaimer
| Include Page | ||||
|---|---|---|---|---|
|
Document Change History
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