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Trenz Electronic TE0711 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, 32 MByte Quad SPI Flash memory for configuration and operation and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/O's are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoM's in 4 x 5 cm form factor follow the same mechanical design rules, thus they are interchangeable.

Block Diagram

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Figure 1: TE0711-01 block diagram.

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1. Artix-7 (15T to 100T) FPGA
2. EN6347QI voltage Regulator 1.0V
3. EN5311QI voltage Regulator 1.8V
4. S25FL256S 32 MByte Quad SPI Flash memory
5. Dual USB to UART/FIFO Bridge (FT2232H)
6. TPS27082L load switch for 3.3V voltage level
7. B2B connector JM1 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
8. B2B connector JM2 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
9. B2B connector JM3 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
10. System Controller CPLD (Lattice LCMXO2-256HC): 256 Macrocell CPLD
11. SiT8008AI 100 MHz reference clock (connected to FPGA bank 14)
12. SiT8008AI 12 MHz reference clock (connected to USB to UART/FIFO Bridge)
13. EEPROM (configuration data for USB to UART/FIFO Bridge)
    
14. TPS3805H33 voltage detector for generating "Power OK"-signal indicating successful power-on-sequencing

Key Features

• Industrial-grade Xilinx Artix-7 (15T to 100T) SoM (System on Module), supported by the free Xilinx Vivado WebPACK tool

• Rugged for shock and high vibration

• FTDI FT2232HQ USB 2.0 High Speed to UART/FIFO

• 32 MByte QSPI Flash memory (with XiP support)

• 100 MHz MEMS oscillator

• Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips

• 178 FPGA I/Os (84 differential pairs) are available on board-to-board connectors

• On-board high-efficiency DC-DC converters

  • 4.0 A x 1.0 V power rail

  • 1.0 A x 1.8 V power rail

  • 1.0 A x 1.5 V power rail

• System management and power sequencing

• eFUSE bit-stream encryption

• AES bit-stream encryption

• User LED

• Evenly-spread supply pins for good signal integrity

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Table 1: Initial TE0711 initial delivery state.

Signals, Interfaces and Pins

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Table 4: Pin-description of System Controller CPLD.

LEDs

On the SoM TE0710 there is a total of 3 LEDS available. Two LEDs are status LEDs, one can freely used in costumer designs. The user LED is routed to the FPGA by the net with the schematic-name 'USERLED'.

When the FPGA is not configured the status LEDs will flash continuously. Finally once FPGA configuration has completed the status LEDs can be used in the user's FPGA design.

LED's

The TE0711 SoM has total of 4 on-board LED's. LED's D1, D2 and D3 are connected to the Xilinx Artix-7 FPGA and can be freely used by user design. LED D4 is the System Controller CPLD status LED.

Table 5: Description of the on-board LEDsLED's.

Clocking

The TE0710 TE0711 is equipped with two MEMS oscillators to provide clock signals for two on-board Ethernet PHY's and DDR3 SDRAM.

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Reference oscillator clock for USB to UART/FIFO Bridge (FT2232H)

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12 MHz

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MEMS oscillator (SiT8008AI-73-XXS-

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100.000000E

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U8 SiT8008AI-73-XXS-100.000000E

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, U8) to provide 100 MHz clock signal for Xilinx Artix-7 FPGA pin P17.

On-board Peripherals

32 MByte

Table 6: Clocks overview

Onboard Peripherals

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Quad SPI Flash Memory

An SPI flash memory S25FL256S (U7) is provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data rate will be dependent on the bus width and clock frequency.

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Power and Power-On Sequence

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Table 76: maximal current of power suppliesTypical power consumption.

Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC/DC converter efficiency (it decreases when VIN/VOUT ratio rises).

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For highest efficiency of on board DC/-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/O's are 3-stated at power-on until System Controller sets STAT_SC2 signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10,12 or 91, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx Artix-7 datasheet DS181 (for Artix7) for additional information. User should also Also check related baseboard documentation when choosing baseboard design for TE0711-01 module.

A 3.3V supply is also needed and must be supplied from the user's PCB. An output 3.3V supply is available on some of the board connector pins (see section 'Power Rails'). The input 3.3VIN will be switched to the internal 3.3V voltage level after the FPGA 1.0V supply is stablehas stabilized. Than 3.3V supply will be available on the B2B connector pins.

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Table 87: Power rails of SoM on B2B connectors.

Bank Voltages

Table 98: Range of FPGA's bank voltages.

See the Artix7 datasheet DS181 for the allowable voltage range.

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Table 109: Differences between variants of Module TE0711-01

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Table 1110: Absolute maximum ratings.

Recommended

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Operating Conditions

Table 1211: Recommended operation operating conditions.

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Industrial grade: -40°C to +85°C.

The module Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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All dimensions are shown in mmmillimeters.

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Figure 3: Physical Dimensions of the TE0711-01 board.

Weight

Table 11: Module weight data.

Revision History

Hardware Revision History

Table 12: Hardware revisions.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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Disclaimer

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