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Table of Contents

Table of Contents

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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx  Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

...

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to TE0728 Resourceshttp://trenz.org/te0728-info for the current online version of this manual and other available documentation.

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    • Note:
  • Xilinx
  • XA7Z020
  • XC7Z020-1CLG484Q (Automotive)
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  • Temperature range: Automotive
  • [XA7Z014S is available on other assembly options]
    • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)

  • Dual-Core ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • 512 MByte DDR3L SDRAM, 16-bit-wide 
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
  • 16 MByte
  • QSPI Flash memory (with XiP support)
  • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • [different size is available on other assembly options]
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • 12 V power supply with watchdog
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
  • Evenly-spread supply pins for good signal integrity

Other assembly options for cost or performance optimization plus high volume prices available on request.

Depending on the customer design, additional cooling might be required.

test

Block Diagram

  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • I/O Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • Power Supply
    • 12 V power supply with watchdog
  • Others:
    • Dimensions: 6 x 6 cm
    • Rugged for shock and high vibration
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
    • Evenly-spread supply pins for good signal integrity

Block Diagram

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Main Components

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  1. 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver  DP83848, U3
  4. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
  5. Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
  6. 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
  7. Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
  8. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
  9. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
  10. 100 MBit Ethernet transceiver  DP83848MPHPEP, U10
  11. 64 Kbit I2C EEPROM, 24LC64, U11
  12. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
  13. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
  14. Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
  15. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
  16. CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
  17. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM2
  18. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM3
  19. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
  20. User LED Green

Initial Delivery State

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  1. DDR3 SDRAM, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver, U3
  4. 100 MBit Ethernet transceiver, U10
  5. User LED Green, D4
  6. Real Time Clock, U7
  7. Standard Clock Oscillators, U5
  8. 64 Kbit I2C EEPROM, U11
  9. CAN Tranceiver, U16
  10. QSPI NOR Flash memory, U13
  11. Standard Clock Oscillators, U14
  12. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
  13. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  14. B2B connector , JM2
  15. B2B connector , JM3
  16. B2B connector , JM1

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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Storage Device

Symbol

Content

Quad SPI Flash

U13

Not Programmed

EEPROMU11Not Programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables,


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Storage device name

Content

Notes

Quad SPI Flash

U13

Empty

DDR3 SDRAMU1Empty
24LC64U11

Control Signals

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  • Overview of Boot Mode, Reset, Enables,

Signal

FPGA BankPinB2BSignal StateBoot Mode

Boot_R

500

E4

J2-11

Low

QSPI

HighSD Card



QSPI
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Signal

B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B

MODE Signal State

Boot Mode

High or open


Signals, Interfaces and Pins

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Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
13
JM1
HRJ148 Single ended (24 Diff)VCCO_13variable from carrier
500
JM1
MIOJ14 Singel ended3.3V
33JM3343.3V

501MIOJ238 Singel endedVMIO1variable from carrier
33HRJ334 Single ended (17 Diff)
35JM320
3.3V
35
JM2
HR
22

J3

J2

20 Single ended (10 Diff)

22 Single ended (11 Diff)

3.3V
501JM238VMIO1MIO1 VREF is connected to resistor divider to support HSTL18

JTAG Interface



Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJM2-12
TDIJM2-10
TDOJM2-8
TCKJM2-6

PS7 UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
SchematicETH1ETH2DirectionNotes
CTREFJ3-57J3-25InMagnetics center tap voltage
TD+J3-58J3-28OutTransfer
TD-J3-56J3-26Out
RD+J3-52J3-22InReceive
RD-J3-50J3-20In
LED1J3-55J3-23OutLED Yellow on carrier, multiple usage-ACK
LED2J3-53J3-21Out
LED3J3-51J3-19OutLED Green on carrier, multiple usage-Link
POWERDOWN/INTL21R20In
RESET_NM15R16InActive low PHY Reset


CAN PHY

CAN pins connections to Board to Board (B2B).

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Chip/Interface
Schematic
IC
B2B
PS7 Peripheral
DirectionNotes
SPI FlashS25FL127SABMFV10QSPI016 MByte Flash
I2C EEPROM24LC64I2C064 Kbit EEPROM
RTC I2CRV-3029I2C0RTC InterruptRV-3029GPIO - MIO0User LEDLED GreenGPIO - MIO7

16 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

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 Temperature Range:

  • Industrial (-40°C to +85°C)
  • Industrial Plus (-40°C to +105°C)
  • Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
  • Automotive AEC-Q100 Grade 2 (-40°C to +105°C)

RTC I2C

...

CANH/CANLJ1-2/J1-4Inout/Inout


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6


MIO Pins

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MIO PinConnected toB2BNotes
MIO0MIO0-RTC interrupt
MIO1...MIO6

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

-SPI Flash
MIO7LED RED-LED
MIO8/MIO9Tx/Rx-CAN Transceiver
MIO10...MIO13IO_0 ... IO_3J1GPIO
MIO14/MIO15SCL/SDA-I2C
MIO16...MIO39-J2GPIO
MIO40...MIO48CLK, Cmd, Data0...Data3, wp, cdJ2SD
MIO48PS_MIO48_501J2LED Red on Carrier
MIO49PS_MIO49_501J2LED Yellow on Carrier
MIO50PS_MIO49_501J2LED Green on Carrier
MIO51PS_MIO51_501J2GPIO
MIO52/MIO53UART_Txd / UART_RxdJ2UART transfer/recieve


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transceiver PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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MIO PinSchematicU7 PinNotes
MIO15SDA5On-board RTC, and EEPROM
MIO14SCL4On-board RTC, and EEPROM

I2C EEPROM

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Chip/InterfaceDesignatorNotes
QSPI FlashU13---
EEPROMU11EEPROM
RTCU7Real Time Clock
DDR3 SDRAMU1Volatile Memory
EthernetU3, U10Two 100 Mbit Ethernet PHY
CAN TransceiverU16---
User LEDD4Green LED
OscillatorsU14, U7, U5Clock Sources


Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

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MIO PinSchematic
U11 Pin
Notes
MIO15SDA3On-board RTC, and EEPROMMIO14SCL1On-board RTC, and EEPROM