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Table of Contents

Table of Contents

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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx  Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

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All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to TE0728 Resourceshttp://trenz.org/te0728-info for the current online version of this manual and other available documentation.

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    • Note:
  • Xilinx
  • XA7Z020
  • XC7Z020-1CLG484Q (Automotive)
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  • Temperature range: Automotive
  • [XA7Z014S is available on other assembly options]
    • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)

  • Dual-Core ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • 512 MByte DDR3L SDRAM, 16-bit-wide 
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
  • 16 MByte
  • QSPI Flash memory (with XiP support)
  • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • [different size is available on other assembly options]
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • 12 V power supply with watchdog
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
  • Evenly-spread supply pins for good signal integrity

Other assembly options for cost or performance optimization plus high volume prices available on request.

Depending on the customer design, additional cooling might be required.

Block Diagram

  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • I/O Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • Power Supply
    • 12 V power supply with watchdog
  • Others:
    • Dimensions: 6 x 6 cm
    • Rugged for shock and high vibration
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
    • Evenly-spread supply pins for good signal integrity

Block Diagram

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Main Components

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Notes :

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  • Add List below

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  1. DDR3 SDRAM, 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver  DP83848transceiver, U3
  4. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
  5. Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
  6. 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
  7. Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
  8. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
  9. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
  10. 100 MBit Ethernet transceiver  DP83848MPHPEP, U10
  11. 64 Kbit I2C EEPROM, 24LC64, U11
  12. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
  13. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
  14. Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
  15. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
  16. CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
  17. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM2
  18. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM3
  19. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
  20. User LED Green

Initial Delivery State

  1. 100 MBit Ethernet transceiver, U10
  2. User LED Green, D4
  3. Real Time Clock, U7
  4. Standard Clock Oscillators, U5
  5. 64 Kbit I2C EEPROM, U11
  6. CAN Tranceiver, U16
  7. QSPI NOR Flash memory, U13
  8. Standard Clock Oscillators, U14
  9. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
  10. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  11. B2B connector , JM2
  12. B2B connector , JM3
  13. B2B connector , JM1

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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Storage

device name

Device

Symbol

Content

Quad SPI Flash

U13
Empty

Not Programmed

24xx64
EEPROMU11Not Programmed

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Configuration Signals

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  • Overview of Boot Mode, Reset, Enables,

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Signal

FPGA BankPinB2B
MIO pin
Signal StateBoot Mode
MIO4

Boot_R

500

E4

J2-11

Low

QSPI

MIO4
HighSD Card

Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B).



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Signal

FPGA BankPinB2B

PS_POR_B

500

B5

JM2-9
PS_SRST_B501C9JM2-2
B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B


Signals, Interfaces and Pins

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Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
13HR
JM1
J148 Single ended (24 Diff)VCCO_13variable from carrier
500
JM1
MIOJ14 Singel ended3.3V
501MIOJ238 Singel endedVMIO1variable from carrier
33HR
JM3
J334 Single ended (17 Diff)3.3V
35
JM3
HR
20

J3

3.3V35JM2

J2

20 Single ended (10 Diff)

22 Single ended (11 Diff)

22

3.3V
501JM238VMIO1MIO1 VREF is connected to resistor divider to support HSTL18