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  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
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          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
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Table of Contents

Table of Contents

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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx  Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

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    • Note:
  • Xilinx
  • XA7Z020
  • XC7Z020-1CLG484Q (Automotive)
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  • Temperature range: Automotive
  • [XA7Z014S is available on other assembly options]
    • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)

  • Dual-Core ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • 512 MByte DDR3L SDRAM, 16-bit-wide 
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
  • 16 MByte
  • QSPI Flash memory (with XiP support)
  • [different size is available on other assembly options]
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • Temperature compensated RTC (real-time clock)
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • I/O Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • Power Supply
    • 12 V power supply with watchdog
  • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • CAN transceiver (PHY)
  • 12 V power supply with watchdog
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • Others:
    • Dimensions: 6 x 6 cm
    • Rugged for shock and high vibration
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
    • Evenly-spread supply pins for good signal integrity

Depending on the customer design, additional cooling might be required.

Block Diagram



Block Diagram

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titleTE0728 block diagram


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Main Components

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Notes :

  • |Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

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Scroll Title
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titleTE0728 main components


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Image Modified




  1. 512 MByte DDR3 SDRAM, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver, U3
  4. 3.5V to 60V step-down converter, U4
  5. Standard Clock Oscillators @ 25MHz, U5
  6. 1.5 A Low Dropout Linear Regulator, U6
  7. Real Time Clock, Micro Crystal @32.768 MHz, U7
  8. 3.5V to 60V step-down converter, U8
  9. 3.5V to 60V step-down converter, U9
  10. 100 MBit Ethernet transceiver, U10
  11. 100 MBit Ethernet transceiver, U10
  12. User LED Green, D4
  13. Real Time Clock, U7
  14. Standard Clock Oscillators, U5
  15. 64 Kbit I2C EEPROM, U11
  16. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, U12
  17. CAN Tranceiver, U16
  18. QSPI NOR 16 MByte QSPI Nor Flash memory, U13
  19. Standard Clock Oscillators @ 50MHzOscillators, U14
  20. Low-Quiescent-Current Priggrammable Programmable Delay Supervisory Circuit, U15
  21. CAN Tranceiver, U16
  22. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  23. B2B connector B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03 , JM2
  24. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03connector , JM3
  25. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
    User LED Greenconnector , JM1

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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titleInitial delivery state of programmable devices on the module

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Storage

device name

Device

Symbol

Content

Quad SPI Flash

U13
Empty

Not Programmed

EEPROMU11Not Programmed

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Configuration Signals

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  • Overview of Boot Mode, Reset, Enables,

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titleBoot process.

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MIO4

Signal

FPGA BankPinB2BMIO pinSignal StateBoot Mode

Boot_R

500

E4

J2-11

Low

QSPI

MIO4HighSD Card

Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B).



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Signal

FPGA BankPinB2B

PS_POR_B

500

B5

JM2-9
PS_SRST_B501C9JM2-2
B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B


Signals, Interfaces and Pins

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Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
13HR
JM1
J148 Single ended (24 Diff)VCCO_13variable from carrier
500MIO
JM1
J14 Singel ended3.3V
501MIOJ2
37
38 Singel endedVMIO1variable from carrier
33HR
JM3
J334 Single ended (17 Diff)3.3V
35
JM3
HR
20

J3

3.3V35JM2

J2

20 Single ended (10 Diff)

22 Single ended (11 Diff)

22

3.3V

JTAG Interface



Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJM2-12
TDIJM2-10
TDOJM2-8
TCKJM2-6

MIO Pins

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titleMIOs pins

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UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53.

On-board Peripherals

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Notes :

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SchematicETH1ETH2DirectionNotes
CTREFJ3-57J3-25InMagnetics center tap voltage
TD+J3-58J3-28OutTransfer
TD-J3-56J3-26Out
RD+J3-52J3-22InReceive
RD-J3-50J3-20In
LED1J3-55J3-23OutLED Yellow on carrier, multiple usage-ACK
LED2J3-53J3-21Out
LED3J3-51J3-19OutLED Green on carrier, multiple usage-Link
POWERDOWN/INTL21R20In
RESET_NM15R16InActive low PHY Reset


CAN PHY

CAN pins connections to Board to Board (B2B).

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SchematicB2BDirectionNotes
CANH/CANLJ1-2/J1-4Inout/Inout


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6


MIO Pins

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Product
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titleOn board peripheralsMIOs pins

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MIO PinConnected toB2B
Chip/Interface
Notes
SPI FlashU1316 MByte FlashEEPROMU1164 Kbit EEPROMRTCU7Real Time ClockDDR3 SDRAMU1Volatile MemoryEthernetU3, U10CAN TransceiverU16User LEDD4Green LED