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<!-- tables have all same width (web max 1200px and pdfPDF full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

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  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
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        orientationportrait
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        sortEnabledfalse
        cellHighlightingtrue

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Table of Contents

Table of Contents

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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx  Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

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    • Note:
  • Xilinx
  • XA7Z020
  • XC7Z020-1CLG484Q (Automotive)
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  • Temperature range: Automotive
  • [XA7Z014S is available on other assembly options]
    • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)

  • Dual-Core ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • 512 MByte DDR3L SDRAM, 16-bit-wide 
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
  • 16 MByte
  • QSPI Flash memory (with XiP support)
  • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • [different size is available on other assembly options]
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • 12 V power supply with watchdog
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
  • Evenly-spread supply pins for good signal integrity

Depending on the customer design, additional cooling might be required.

Block Diagram

  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • I/O Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • Power Supply
    • 12 V power supply with watchdog
  • Others:
    • Dimensions: 6 x 6 cm
    • Rugged for shock and high vibration
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
    • Evenly-spread supply pins for good signal integrity

Block Diagram

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titleTE0728 block diagram
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titleTE0728 block diagram


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draw.io Diagram
borderfalse
viewerToolbartrue
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revision25


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Main Components

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Notes :

  • |Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

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titleTE0728 main components


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draw.io Diagram
falsewidth
borderfalse
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lboxfalse
diagramWidth633
revision117350


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Image Modified




  1. 512 MByte DDR3 SDRAM, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver, U3
  4. Standard Clock Oscillators @ 25MHz, U5
  5. 1.5 A Low Dropout Linear Regulator, U6
  6. Real Time Clock, Micro Crystal @32.768 MHz, U7
  7. 100 MBit Ethernet transceiver, U10
  8. User LED Green, D4
  9. Real Time Clock, U7
  10. Standard Clock Oscillators, U5100 MBit Ethernet transceiver, U10
  11. 64 Kbit I2C EEPROM, U11
  12. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, U12
  13. CAN Tranceiver, U16
  14. QSPI NOR 16 MByte QSPI Nor Flash memory, U13
  15. Standard Clock Oscillators @ 50MHzOscillators, U14
  16. Low-Quiescent-Current Priggrammable Programmable Delay Supervisory Circuit, U15
  17. CAN Tranceiver, U16Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  18. B2B connector , JM2
  19. B2B connector , JM3
  20. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
    User LED Greenconnector , JM1

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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titleInitial delivery state of programmable devices on the module

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Storage Device

Symbol

Content

Quad SPI Flash

U13

Not Programmed

EEPROMU11Not Programmed

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Configuration Signals

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  • Overview of Boot Mode, Reset, Enables,

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titleBoot process.

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Signal

FPGA BankPinB2BSignal StateBoot Mode

Boot_R

500

E4

J2-11

Low

QSPI

HighSD Card



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titleReset process.

Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B)  connected to VMIO, it means after power on the PS will be reset.

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Signal

B2BI/ONote
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Signal

B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B


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Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:

22
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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
13HRJ148 Single ended (24 Diff)VCCO_13variable from carrier
500MIOJ14 Singel ended3.3V
501MIOJ2
37
38 Singel endedVMIO1variable from carrier
33HRJ334 Single ended (17 Diff)3.3V
35HR

J3

J2

20

Single ended (10 Diff)

22 Single ended (11 Diff)

3.3V35J2

3.3V

JTAG Interface



Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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titleJTAG pins connectionEthernet PHY B2B connectors.

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JTAG Signal
Schematic
B2B Pin
ETH1
TMS
ETH2
J2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6

MIO Pins

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titleMIOs pins

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DirectionNotes
CTREFJ3-57J3-25InMagnetics center tap voltage
TD+J3-58J3-28OutTransfer
TD-J3-56J3-26Out
RD+J3-52J3-22InReceive
RD-J3-50J3-20In
LED1J3-55J3-23OutLED Yellow on carrier, multiple usage-ACK
LED2J3-53J3-21Out
LED3J3-51J3-19OutLED Green on carrier, multiple usage-Link
POWERDOWN/INTL21R20In
RESET_NM15R16InActive low PHY Reset


CAN PHY

CAN pins connections to Board to Board (B2B).

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SchematicB2BDirectionNotes
CANH/CANLJ1-2/J1-4Inout/Inout


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
Scroll Title
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titleOn board peripherals

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Chip/InterfaceProductNotes
SPI FlashU1316 MByte Flash
EEPROMU1164 Kbit EEPROM
RTCU7Real Time Clock
DDR3 SDRAMU1Volatile Memory
EthernetU3, U10Two 100 Mbit Ethernet
CAN TransceiverU16
User LEDD4Green LED

Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

...

anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

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JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6


MIO Pins

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MIO PinConnected toB2BNotes
MIO0MIO0-RTC interrupt
MIO1...MIO6

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

-SPI Flash
MIO7LED RED-LED
MIO8/MIO9Tx/Rx-CAN Transceiver
MIO10...MIO13IO_0 ... IO_3J1GPIO
MIO14/MIO15SCL/SDA-I2C
MIO16...MIO39-J2GPIO
MIO40...MIO48CLK, Cmd, Data0...Data3, wp, cdJ2SD
MIO48PS_MIO48_501J2LED Red on Carrier
MIO49PS_MIO49_501J2LED Yellow on Carrier
MIO50PS_MIO49_501J2LED Green on Carrier
MIO51PS_MIO51_501J2GPIO
MIO52/MIO53UART_Txd / UART_RxdJ2UART transfer/recieve


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transceiver PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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titleOn board peripherals

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RTC 

The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC intruppt is connected to MIO0 connected to Bank 500, pin G6.

Pin
Scroll Title
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titleI2C interface MIOs and pins

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Chip/InterfaceDesignator
MIO PinSchematic
Notes
MIO15
QSPI Flash
SDA
U13
U7-5On-board RTC, and EEPROMMIO14SCLU7-4On-board RTC, and EEPROM