Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

HTML
<!-- tables have all same width (web max 1200px and pdfPDF full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

...

Page properties
hiddentrue
idComments

Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf PDF export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefaultstyle
        widthssortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant consistent across TRMs. A An incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

...

Page properties
hiddentrue
idComments

Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

...

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating an Automotive Xilinx  Zynq-7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , DDR3L SDRAMDDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

...

Page properties
hiddentrue
idComments
    • Note:
  • Xilinx
  • XA7Z020
  • XC7Z020-1CLG484Q (Automotive) [
  • Z7014S is
  • XA7Z014S is available on
  • demand]
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  • Temperature range: Automotive
  • other assembly options]
    • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)

  • Dual-Core ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • DDR3L SDRAM, 16-bit-width [
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
  • QSPI Flash memory (with XiP support) [different size is available on other assembly options]
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • Temperature compensated RTC (real-time clock)
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • CAN transceiver (PHY)
  • I/O Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • Power Supply
    • 12 V power supply with watchdog
  • Others:
    • Dimensions: 6 x 6 cm
    • Rugged for shock and high vibration
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
    • Evenly-spread supply pins for good signal integrity

Depending on the customer design, additional cooling might be required.


Block Diagram

Scroll Title
anchorFigure_OV_BD
titleTE0728 block diagram


Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalsediagramDisplayName
lboxtrue
revision14
diagramNameTE0728_OV_BD
simpleViewerfalse
widthlinksauto
tbstylehidden
lboxtrue
diagramWidth641
revision25


Scroll Only


Main Components

Page properties
hiddentrue
idComments

Notes :

  • |Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

...

Scroll Title
anchorFigure_OV_MC
titleTE0728 main components


Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalsediagramDisplayNamelboxfalse
revision44
diagramNameTE0728_MC2
simpleViewertrue
width640
linksauto
tbstylehidden
lboxfalse
diagramWidth633
revision117350


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue



...

  1. DDR3 SDRAM, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver, U3
  4. 100 MBit Ethernet transceiver, U10
  5. User LED Green, D4
  6. Real Time Clock, Micro Crystal @32.768 MHz, U7
  7. Standard Clock Oscillators @ 25MHzOscillators, U5
  8. 64 Kbit I2C EEPROM, U11
  9. CAN Tranceiver, U16
  10. QSPI Nor NOR Flash memory, U13
  11. Standard Clock Oscillators @ 50MHzOscillators, U14
  12. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
  13. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  14. B2B connector , JM2
  15. B2B connector , JM3
  16. B2B connector , JM1

Initial Delivery State

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

Scroll Title
anchorTable_
Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
widthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

Storage Device

Symbol

Content

Quad SPI Flash

U13

Not Programmed

EEPROMU11Not Programmed


...

Page properties
hiddentrue
idComments
  • Overview of Boot Mode, Reset, Enables,

...


Scroll Title
anchorTable_OV_BP
titleBoot process.

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

FPGA BankPinB2BSignal StateBoot Mode

Boot_R

500

E4

J2-11

Low

QSPI

HighSD Card



Scroll Title
anchorTable_OV_RST
titleReset process.

Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B)  connected to VMIO, it means after power on the PS will be reset.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault

Scroll Title
anchorTable_OV_RST
titleReset process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
stylewidthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B


...

Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA FPGA bank number and number of I/O signals connected to the B2B connector:

22
Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
13HRJ148 Single
-end,
ended (24 Diff)VCCO_13variable from carrier
500
HR
MIOJ14 Singel ended3.3V
501
HR
MIOJ2
37
38 Singel endedVMIO1variable from carrier
33HRJ334 Single ended (17 Diff)3.3V
35HR

J3

203.3V35HRJ2

J2

20 Single ended (10 Diff)

22 Single ended (11 Diff)

3.3V


Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.

Scroll Title
anchorTable_SIP_B2B_Eth
titleEthernet PHY B2B connectors.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
widthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicETH1ETH2Direction
Pullup
Notes
CTREFJ3-57J3-25InMagnetics center tap voltage
TD+J3-58J3-28Out
on-board
Transfer
TD-J3-56J3-26Out
on-boardRD+

RD+J3-52J3-22In
on-board
Receive
Recieve
RD-J3-50J3-20In
on-board

LED1J3-55J3-23Out
on-board
LED Yellow on carrier, multiple usage-ACK
LED2J3-53J3-21Out
on-board

LED3J3-51J3-19Out
on-board
LED Green on carrier, multiple usage-Link
POWERDOWN/INTL21R20In
on-chip

RESET_NM15R16In
on-chip
Active low PHY Reset


CAN PHY

CAN pins connections to Board to Board (B2B).

Scroll Title
anchorTable_SIP_B2B_CAN
titleCAN B2B connectors.

Scroll Table Layout
style
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
widthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicB2BMIO PinDirectionNotes
CANH/CANLJ1-2/J1-4-Inout/InoutTX/RXMIO8/MIO9Out/In


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

Scroll Table Layout
style
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
widthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6


...

Pullup
Scroll Title
anchorTable_OBP_MIOs
titleMIOs pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
widthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO Pin
Schematic
Connected toB2B
Direction
Notes
MIO0MIO0-
Enable
RTC interrupt
MIO1...MIO6

SPI_CS

-OutEnableSPI FlashMIO2-5SPI

, SPI_DQ0... SPI_DQ3

/M0...M3

-InoutDisable

SPI

FlashMIO6SPI

_SCK

/M4

-
OutDisable
SPI Flash
clock
MIO7LED RED-
OutDisable
LED
MIO8
TX-OutDisableCAN Transceiver
/MIO9
RX
Tx/Rx-
OutEnable
CAN Transceiver
MIO10...MIO13IO_0 ... IO_3J1
-7
InoutEnable
GPIO
MIO11IO_1J1-9InoutEnableGPIOMIO12IO_2J1-11InoutEnableGPIOMIO13IO_3J1-13InoutEnableGPIOMIO14SCL-InoutEnableI2CMIO15SDA-InoutEnableI2CMIO16-J2-17InoutEnableGPIOMIO17-J2-18InoutEnableGPIOMIO18-J2-27InoutEnableGPIOMIO19-J2-23InoutEnableGPIOMIO20-J2-28InoutEnableGPIOMIO21-J2-22InoutEnableGPIOMIO22-J2-26InoutEnableGPIOMIO23-J2-20InoutEnableGPIOMIO24-J2-24InoutEnableGPIOMIO25-J2-21InoutEnableGPIOMIO26-J2-25InoutEnableGPIOMIO27-J2-19InoutEnableGPIOMIO28Tx_clkJ2-51OutEnableETHMIO29Txd0J2-44OutEnableETHMIO30Txd1J2-49OutEnableETHMIO31Txd2J2-43OutEnableETHMIO32Txd3J2-42OutEnableETHMIO33Tx_ctlJ2-46OutEnableETHMIO34Rx_clkJ2-48InEnableETHMIO35Rxd0J2-47InEnableETHMIO36Rxd1J2-41InEnableETHMIO37Rxd2J2-52InEnableETHMIO38Rxd3J2-45InEnableETHMIO39Rx_ctlJ2-50InEnableETHMIO40CLKJ2-34InoutDisableSD on carrierMIO41CmdJ2-29InoutDisableSD on carrierMIO42Data0J2-37InoutDisableSD on carrierMIO43Data1J2-40InoutDisableSD on carrierMIO44Data2J2-32InoutDisableSD on carrierMIO45Data3J2-31InoutDisableSD on carrierMIO46wpJ2-35InEnableSD on carrierMIO47cdJ2-33InEnableSD on carrierMIO48MIO48J2-30OutEnableLED Red on CarrierMIO49MIO49J2-38OutEnableLED Yellow on CarrierMIO50MIO50J2-36OutEnableLED Green on CarrierMIO51MIO51J2-39InoutDisableGPIOMIO52UART_TxdJ2-15OutEnableUART transferMIO53UART_RxdJ2-16InEnableUART receive