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Table of Contents

Table of Contents

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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating an Automotive Xilinx  Zynq-7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , DDR3L SDRAMDDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

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    • Note:
  • Xilinx
  • XA7Z020
  • XC7Z020-1CLG484Q (Automotive) [
  • Z7014S is
  • XA7Z014S is available on
  • demand]
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  • Temperature range: Automotive
  • other assembly options]
    • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)

  • Dual-Core ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • DDR3L SDRAM, 16-bit-width [
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
  • QSPI Flash memory (with XiP support) [different size is available on other assembly options]
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • Temperature compensated RTC (real-time clock)
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • 76 single ended
  • I/O
  • , 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectorsCAN transceiver (PHY)
  • Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • Power Supply
    • 12 V power supply with watchdog
  • Others:
    • Dimensions: 6 x 6 cm
    • Rugged for shock and high vibration
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
    • Evenly-spread supply pins for good signal integrity

Depending on the customer design, additional cooling might be required.

Block Diagram



Block Diagram

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Main Components

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  • Add List below

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titleTE0728 main components


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  1. DDR3 SDRAM, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver, U3
  4. 100 MBit Ethernet transceiver, U10
  5. User LED Green, D4
  6. Real Time Clock, Micro Crystal , U7
  7. Standard Clock Oscillators, U5
  8. 64 Kbit I2C EEPROM, U11
  9. CAN Tranceiver, U16
  10. QSPI Nor NOR Flash memory, U13
  11. Standard Clock Oscillators, U14
  12. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
  13. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  14. B2B connector , JM2
  15. B2B connector , JM3
  16. B2B connector , JM1

Initial Delivery State

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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Storage Device

Symbol

Content

Quad SPI Flash

U13

Not Programmed

EEPROMU11Not Programmed


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  • Overview of Boot Mode, Reset, Enables,

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Signal

FPGA BankPinB2BSignal StateBoot Mode

Boot_R

500

E4

J2-11

Low

QSPI

HighSD Card



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titleReset process.

Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B)  connected to VMIO, it means after power on the PS will be reset.

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Signal

B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B


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Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:

22
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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
13HRJ148 Single
-end,
ended (24 Diff)VCCO_13variable from carrier
500MIOJ14 Singel ended3.3V
501MIOJ2
37
38 Singel endedVMIO1variable from carrier
33HRJ334 Single ended (17 Diff)3.3V
35HR

J3

J2

20

Single ended (10 Diff)

22 Single ended (11 Diff)

3.3V35HRJ2

3.3V


Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.

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SchematicETH1ETH2Direction
Pullup
Notes
CTREFJ3-57J3-25InMagnetics center tap voltage
TD+J3-58J3-28Out
on-board
Transfer
TD-J3-56J3-26Out
on-board

RD+J3-52J3-22In
on-boardRecieve
Receive
RD-J3-50J3-20In
on-board

LED1J3-55J3-23Out
on-board
LED Yellow on carrier, multiple usage-ACK
LED2J3-53J3-21Out
on-board

LED3J3-51J3-19Out
on-board
LED Green on carrier, multiple usage-Link
POWERDOWN/INTL21R20In
on-chip

RESET_NM15R16In
on-chip
Active low PHY Reset


CAN PHY

CAN pins connections to Board to Board (B2B).

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MIO Pin
SchematicB2BDirectionNotes
CANH/CANLJ1-2/J1-4-Inout/InoutTX/RXMIO8/MIO9Out/In


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6


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MIO PinSchematicConnected toB2BNotes
MIO0MIO0-RTC interrupt
MIO1...MIO6

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

-SPI Flash
MIO7LED RED-LED
MIO8/MIO9Tx/Rx-CAN Transceiver
MIO10...MIO13IO_0 ... IO_3J1GPIO
MIO14/MIO15SCL/SDA-I2C
MIO16...MIO27MIO39-J2GPIO
MIO28MIO40...MIO39MIO48

Tx_clk, Txd0...Txd3, Tx_ctl

Rx_clk, Rxd0...Rxd3, Rx_ctl

J2ETHMIO40...MIO48CLK, Cmd, CLK, Cmd, Data0...Data3, wp, cdJ2SD
MIO48PS_MIO48_501J2LED Red on Carrier
MIO49PS_MIO49_501J2LED Yellow on Carrier
MIO50MIO50PS_MIO49_501J2LED Green on Carrier
MIO51PS_MIO51_501J2GPIO
MIO52/MIO53UART_Txd / UART_RxdJ2UART transfer/recieve


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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever Transceiver PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

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Chip/InterfaceProductDesignatorNotes
QSPI FlashU13---
EEPROMU11EEPROM
RTCU7Real Time Clock
DDR3 SDRAMU1Volatile Memory
EthernetU3, U10Two 100 Mbit Ethernet PHY
CAN TransceiverU16---
User LEDD4Green LED
OscillatorsU14, U7, U5Clock Sources


Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

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U13-A1U13-E4U13-A3U13-A4
MIO PinSchematicPinNotes
MIO1SPI_CS
MIO2SPI_DQ0/M0U13-A2
MIO3SPI_DQ1/M1U13-F6
MIO4SPI_DQ2/M2
MIO5SPI_DQ3/M3
MIO6SPI_SCK/M4


RTC 

The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC intruppt interrupt is connected to MIO0 connected to Bank 500 through pin G6.

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MIO PinI2C AddressDesignatorNotes
MIO14...15
0x68
0x56U7
---
Slave address


EEPROM

The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

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MIO PinI2C AddressDesignatorNotes
MIO14...150xA00x50U11---Slave address


LEDs

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SchematicDesignatorColorConnected toActive LevelIO Standard
D9GreenDONELownot applicable
D8REDMIO7Highnot applicable
D4GreenBank 33 - V18HighLVCMOS33


DDR3 SDRAM

The TE0728 SoM has a volatile DDR3 SDRAM, 256Mx16bit (512MB), IC for storing user application code and data. Size of DDR3 can be varied in different assembly versions. 

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

  • Part number: NT5CB256M16CP-DIH
  • Supply voltage: 1.5V
  • Organization: 256M x 16 bits

DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1066 Mb/s.

Ethernet

There are two 100 MBit There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrument on Instrumen on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source sources is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

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titleEthernet PHY to Zynq SoC connections

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BankSignal Name
Schematic
ETH1ETH2
Pullup
Signal Description
NotesJ3
34
CTREF
ETH-
57
RST
J3-25Magnetics center tap voltageTD+J3-58J3-28on-boardTD-J3-56J3-26on-boardRD+J3-52J3-22on-boardRD-J3-50J3-20on-boardLED1J3-55J3-23on-boardLED Yellow on Carrier - ACKLED2J3-53J3-21on-boardSpeedLED3J3-51J3-19on-boardLED Green on Carrier- LinkPOWERDOWN/INTL21R20on-chipRESET_NM15R16on-chip