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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating an Automotive Xilinx  Zynq-7 FPGA, two Ethernet transceivers (PHY) , DDR3L SDRAMDDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

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• Xilinx
XA7Z020
• XC7Z020-1CLG484Q (Automotive) [XA7Z014S is available on other assembly options]
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  Temperature range: Automotive
  • • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)
      
  • Dual-Core ARM Cortex-A9 MPCore
    
  • 2 x 100 MBit Ethernet transceiver (PHY)
  DDR3L SDRAM, 16-bit-width
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
  • QSPI Flash memory (with XiP support) [different size is available on other assembly options]
  Plug-
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • Temperature compensated RTC (real-time clock)
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  76 single ended
  • I/O
  , 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • CAN transceiver (PHY)
  • Power Supply
    • • 12 V power supply with watchdog
    • Others:
      • Dimensions: 6 x 6 cm
      • Rugged for shock and high vibration
      • On-board high-efficiency DC-DC converters
      • System management and power sequencing
      • eFUSE bit-stream encryption
      • AES bit-stream encryption
    • Temperature compensated RTC (real-time clock)
    • Three user LEDs
    • • Evenly-spread supply pins for good signal integrity
        

    Depending on the customer design, additional cooling might be required.

    • • 
        

    Block Diagram

    Scroll Title
    anchor Figure_OV_BD title TE0728 block diagram
    Scroll Ignore draw.io Diagram diagramDisplayNamewidth border false viewerToolbar true fitWindow false lbox true revision 15 diagramName TE0728_OV_BD simpleViewer false links auto tbstyle hidden lbox true diagramWidth 641 revision 25 Scroll Only

    Main Components

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    Notes : |Picture of the PCB (top and bottom side) with labels of important components Add List below

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    Scroll Title
    anchor Figure_OV_MC title TE0728 main components
    Scroll Ignore draw.io Diagram border false viewerToolbar true fitWindow false diagramDisplayName lbox false revision 44 diagramName TE0728 diagramName TE0728_MC2 simpleViewer true width 640 links auto tbstyle hidden lbox false diagramWidth 633 revision 117350 Scroll Only scroll-pdf true scroll-office true scroll-chm true scroll-docbook true scroll-eclipsehelp true scroll-epub true scroll-html true

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    Scroll Title
    anchor Table_OV_IDS title Initial delivery state of programmable devices on the module
    Scroll Table Layout style orientation portrait sortDirection ASC repeatTableHeaders default widths sortByColumn 1 sortEnabled false cellHighlighting true Storage Device Symbol Content Quad SPI Flash U13 Not Programmed EEPROM U11 Not Programmed

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    Overview of Boot Mode, Reset, Enables,

    Boot Mode

    
    

    Scroll Title
    anchor Table_OV_BP title Boot process.
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal FPGA Bank Pin B2B Signal State Boot Mode Boot_R 500 E4 J2-11 Low QSPI High SD Card

    
    

    Scroll Title
    anchor Table_OV_RST title Reset process.

    Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B)  connected to VMIO, it means after power on the PS will be reset.

    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default
    Scroll Title
    anchor Table_OV_RST title Reset process.
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal B2B I/O Note Reset J2-7 Input Comes from Carrier RST_OUT J2-9 Output PS_PROB_B

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    Board to Board (B2B) I/Os

    TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

    FPGA FPGA bank number and number of I/O signals connected to the B2B connector:

    Scroll Title
    anchor Table_SIP_B2B title General PL I/O to B2B connectors information
    Scroll Table Layout widths orientation portrait sortDirection ASC repeatTableHeaders default style sortByColumn 1 sortEnabled false cellHighlighting true FPGA Bank Type B2B Connector I/O Signal Count Voltage Level Notes 13 HR J1 48 Single -end ended (24 Diff) VCCO_13 variable from carrier 500 MIO J1 4 Single end Singel ended 3.3V 501 MIO J2 38 Single end Singel ended VMIO1 variable from carrier 33 HR J3 34 Single end ended (17 Diff) 3.3V 35 HR J3 J2 20 Single end ended (10 Diff) 22 Single end ended (11 Diff) 3.3V

    Ethernet PHY

    Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.

    Scroll Title
    anchor Table_SIP_B2B_Eth title Ethernet PHY B2B connectors.
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Schematic ETH1 ETH2 Direction Notes CTREF J3-57 J3-25 In Magnetics center tap voltage TD+ J3-58 J3-28 Out Transfer TD- J3-56 J3-26 Out RD+ J3-52 J3-22 In RecieveReceive RD- J3-50 J3-20 In LED1 J3-55 J3-23 Out LED Yellow on carrier, multiple usage-ACK LED2 J3-53 J3-21 Out LED3 J3-51 J3-19 Out LED Green on carrier, multiple usage-Link POWERDOWN/INT L21 R20 In RESET_N M15 R16 In Active low PHY Reset

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    Scroll Title
    anchor Table_SIP_B2B_CAN title CAN B2B connectors.
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Schematic B2B MIO Pin Direction Notes CANH/CANL J1-2/J1-4 - Inout/Inout

    JTAG Interface

    JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

    Scroll Title
    anchor Table_SIP_JTG title JTAG pins connection
    Scroll Table Layout widths orientation portrait sortDirection ASC repeatTableHeaders default style sortByColumn 1 sortEnabled false cellHighlighting true JTAG Signal B2B Pin TMS J2-12 TDI J2-10 TDO J2-8 TCK J2-6

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    Scroll Title
    anchor Table_OBP_MIOs title MIOs pins
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin Connected to B2B Notes MIO0 MIO0 - RTC interrupt MIO1...MIO6 SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK - SPI Flash MIO7 LED RED - LED MIO8/MIO9 Tx/Rx - CAN Transceiver MIO10...MIO13 IO_0 ... IO_3 J1 GPIO MIO14/MIO15 SCL/SDA - I2C MIO16...MIO27MIO39 - J2 GPIO MIO28MIO40...MIO39MIO48 CLK, Cmd, Data0Tx_clk, Txd0...Txd3, Tx_ctl Rx_clk, Rxd0...Rxd3, Rx_ctl J2 ETH MIO40...MIO48 CLK, Cmd, Data0...Data3, wp, Data3, wp, cd J2 SD MIO48 PS_MIO48_501 J2 LED Red on Carrier MIO49 PS_MIO49_501 J2 LED Yellow on Carrier MIO50 PS_MIO49_501 J2 LED Green on Carrier MIO51 PS_MIO51_501 J2 GPIO MIO52/MIO53 UART_Txd / UART_Rxd J2 UART transfer/recieve

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    Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever Transceiver PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

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    Scroll Title
    anchor Table_OBP title On board peripherals
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Chip/Interface Designator Notes QSPI Flash U13 --- EEPROM U11 EEPROM RTC U7 Real Time Clock DDR3 SDRAM U1 Volatile Memory Ethernet U3, U10 Two 100 Mbit Ethernet PHY CAN Transceiver U16 --- User LED D4 Green LED Oscillators U14, U7, U5 Clock Sources

    Quad SPI Flash Memory

    On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

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    Scroll Title
    anchor Table_OBP_SPI title Quad SPI interface MIOs and pins
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true PinU13-A1U13-F6 MIO Pin Schematic Notes MIO1 SPI_CS MIO2 SPI_DQ0/M0 U13-A2 MIO3 SPI_DQ1/M1 MIO4 SPI_DQ2/M2 U13-E4 MIO5MIO5 SPI_DQ3/M3 U13-A3 MIO6 SPI_SCK/M4 U13-A4

    RTC 

    The RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

    RTC intruppt interrupt is connected to MIO0 connected to Bank 500 through pin G6.

    Scroll Title
    anchor Table_OBP_I2C_RTC title I2C Address for RTC
    Scroll Table Layout widths orientation portrait sortDirection ASC repeatTableHeaders default style sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin I2C Address Designator Notes MIO14...15 0xAD / 0xAC0x56 U7 Read/ WriteSlave address

    EEPROM

    The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

    Scroll Title
    anchor Table_OBP_I2C_EEPROM title I2C address for EEPROM
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin I2C Address Designator Notes MIO14...15 0xA1/0xA00x50 U11 Read/WriteSlave address

    LEDs

    Scroll Title
    anchor Table_OBP_LED title On-board LEDs
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Color Connected to Active Level D9 Green DONE Low D8 RED MIO7 High D4 Green Bank 33 - V18 High

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    DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1066 Mb/s.

    Ethernet

    There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrumen on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source sources is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

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    Scroll Title
    anchor Table_OBP_ETH title Ethernet PHY to Zynq SoC connections
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Bank Signal Name ETH1 ETH2 Signal Description 34 ETH-RST M15 R16 Ethernet reset, active-low. 34 ETH_COL L16 P20 34 MDC P16 T17 Ethernet management clock. 34 MDIO M16 T16 Ethernet management data. 34 ETH_TX_D0 J22 N22 Ethernet transmit data 0. Output to Ethernet PHY. 34 ETH_TX_D1 M17 P21 Ethernet transmit data 1. Output to Ethernet PHY. 34 ETH_TX_D2 K21 P22 Ethernet transmit data 2. Output to Ethernet PHY. 34 ETH_TX_D3 M22 R21 Ethernet transmit data 3. Output to Ethernet PHY. 34 ETH_TX_EN J21 M21 Ethernet transmit enable. 34 ETH_RX_D0 L17 R18 Ethernet receive data 0. Input from Ethernet PHY.  34 ETH_RX_D1 K18 R19 Ethernet receive data 1. Input from Ethernet PHY.  34 ETH_RX_D2 J18 T18 Ethernet receive data 2. Input from Ethernet PHY.  34 ETH_RX_D3 J20 T19 Ethernet receive data 3. Input from Ethernet PHY.  34 ETH_RX_DV N17 P15 Ethernet receive data valid.

    CAN Transceiver
    

    Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 

    Pin

    Scroll Title
    anchor Table_OBP_CAN title CAN Tranciever interface MIOs
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Bank Signal name	MIO Pin	Schematic

    	Notes

    MIO8

    500

    D - Tx

    U16-1

    Driver Input

    MIO9

    500

    R - Rx

    U16-4

    Reciever Output