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  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
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          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
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        • "Figure_PWR_PS" for Power Sequence
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Table of Contents

Table of Contents

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Notes :

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx  Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

...

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

...

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    • Note:
  • Xilinx
  • XA7Z020
  • XC7Z020-1CLG484Q (Automotive)
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  • Temperature range: automotive
  • [XA7Z014S is available on other assembly options]
    • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)
  • Dual-Core
  • 2 x
  • ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • 512 MByte DDR3L SDRAM, 16-bit-wide 
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
  • 16 MByte
  • QSPI Flash memory (with XiP support) [different size is available on other assembly options]
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • Temperature compensated RTC (real-time clock)
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • CAN transceiver (PHY)
  • I/O Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • Power Supply
    • 12 V power supply with watchdog
  • Others:
    • Dimensions: 6 x 6 cm
    • Rugged for shock and high vibration
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
  • Evenly-spread
    • Evenly-spread supply pins for good signal integrity

  • Other assembly options for cost or performance optimization plus high volume prices available on request.Depending on the customer design, additional cooling might be required.


Block Diagram

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TE0728
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Main Components

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Notes :

  • |Picture of the PCB (top and bottom side) with labels of important components
  • Add List below

...

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titleTE... TE0728 main components


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  1. ...

  2. ...

  3. ...

Initial Delivery State


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  1. DDR3 SDRAM, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver, U3
  4. 100 MBit Ethernet transceiver, U10
  5. User LED Green, D4
  6. Real Time Clock, U7
  7. Standard Clock Oscillators, U5
  8. 64 Kbit I2C EEPROM, U11
  9. CAN Tranceiver, U16
  10. QSPI NOR Flash memory, U13
  11. Standard Clock Oscillators, U14
  12. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
  13. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  14. B2B connector , JM2
  15. B2B connector , JM3
  16. B2B connector , JM1

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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Scroll Title
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titleInitial delivery state of programmable devices on the module.

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Storage device nameDevice

Symbol

Content

Notes

..

..

..
OTP Flash areaEmptyNot programmed.

...

Quad SPI Flash

U13

Not Programmed

EEPROMU11Not Programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables,

Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector typ (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier us only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Subsections...

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

16 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

RTC I2C

User LED

...

512 Mbyte DDR3L SDRAM

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

...

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Signal

FPGA BankPinB2BSignal StateBoot Mode

Boot_R

500

E4

J2-11

Low

QSPI

HighSD Card



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Signal

B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
13HRJ148 Single ended (24 Diff)VCCO_13variable from carrier
500MIOJ14 Singel ended3.3V
501MIOJ238 Singel endedVMIO1variable from carrier
33HRJ334 Single ended (17 Diff)3.3V
35HR

J3

J2

20 Single ended (10 Diff)

22 Single ended (11 Diff)

3.3V


Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.

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SchematicETH1ETH2DirectionNotes
CTREFJ3-57J3-25InMagnetics center tap voltage
TD+J3-58J3-28OutTransfer
TD-J3-56J3-26Out
RD+J3-52J3-22InReceive
RD-J3-50J3-20In
LED1J3-55J3-23OutLED Yellow on carrier, multiple usage-ACK
LED2J3-53J3-21Out
LED3J3-51J3-19OutLED Green on carrier, multiple usage-Link
POWERDOWN/INTL21R20In
RESET_NM15R16InActive low PHY Reset


CAN PHY

CAN pins connections to Board to Board (B2B).

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SchematicB2BDirectionNotes
CANH/CANLJ1-2/J1-4Inout/Inout


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6


MIO Pins

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MIO PinConnected toB2BNotes
MIO0MIO0-RTC interrupt
MIO1...MIO6

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

-SPI Flash
MIO7LED RED-LED
MIO8/MIO9Tx/Rx-CAN Transceiver
MIO10...MIO13IO_0 ... IO_3J1GPIO
MIO14/MIO15SCL/SDA-I2C
MIO16...MIO39-J2GPIO
MIO40...MIO48CLK, Cmd, Data0...Data3, wp, cdJ2SD
MIO48PS_MIO48_501J2LED Red on Carrier
MIO49PS_MIO49_501J2LED Yellow on Carrier
MIO50PS_MIO49_501J2LED Green on Carrier
MIO51PS_MIO51_501J2GPIO
MIO52/MIO53UART_Txd / UART_RxdJ2UART transfer/recieve


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transceiver PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Chip/InterfaceDesignatorNotes
QSPI FlashU13---
EEPROMU11EEPROM
RTCU7Real Time Clock
DDR3 SDRAMU1Volatile Memory
EthernetU3, U10Two 100 Mbit Ethernet PHY
CAN TransceiverU16---
User LEDD4Green LED
OscillatorsU14, U7, U5Clock Sources


Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

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MIO PinSchematicNotes
MIO1SPI_CS
MIO2SPI_DQ0/M0
MIO3SPI_DQ1/M1
MIO4SPI_DQ2/M2
MIO5SPI_DQ3/M3
MIO6SPI_SCK/M4


RTC 

The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC interrupt is connected to MIO0 connected to Bank 500 through pin G6.

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MIO PinI2C AddressDesignatorNotes
MIO14...150x56U7Slave address


EEPROM

The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

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MIO PinI2C AddressDesignatorNotes
MIO14...150x50U11Slave address


LEDs

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DesignatorColorConnected toActive Level
D9GreenDONELow
D8REDMIO7High
D4GreenBank 33 - V18High


DDR3 SDRAM

The TE0728 SoM has a volatile DDR3 SDRAM, 256Mx16bit (512MB), IC for storing user application code and data. Size of DDR3 can be varied in different assembly versions.

  • Part number: NT5CB256M16CP-DIH
  • Supply voltage: 1.5V
  • Organization: 256M x 16 bits

DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1066 Mb/s.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrumen on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz sources is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

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titleEthernet PHY to Zynq SoC connections

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BankSignal NameETH1ETH2Signal Description
34ETH-RSTM15R16Ethernet reset, active-low.
34ETH_COLL16P20
34MDCP16T17

Ethernet management clock.

34MDIOM16T16Ethernet management data.
34ETH_TX_D0J22N22Ethernet transmit data 0. Output to Ethernet PHY.
34ETH_TX_D1M17P21Ethernet transmit data 1. Output to Ethernet PHY.
34ETH_TX_D2K21P22Ethernet transmit data 2. Output to Ethernet PHY.
34ETH_TX_D3M22R21Ethernet transmit data 3. Output to Ethernet PHY.
34ETH_TX_ENJ21M21Ethernet transmit enable.
34ETH_RX_D0L17R18Ethernet receive data 0. Input from Ethernet PHY. 
34ETH_RX_D1K18R19Ethernet receive data 1. Input from Ethernet PHY. 
34ETH_RX_D2J18T18Ethernet receive data 2. Input from Ethernet PHY. 
34ETH_RX_D3J20T19Ethernet receive data 3. Input from Ethernet PHY. 
34ETH_RX_DVN17P15Ethernet receive data valid.


CAN Transceiver

Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 

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BankSignal nameNotes
500D - TxDriver Input
500R - RxReciever Output


Oscillators

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titleOsillators

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DesignatorDescriptionFrequencyUsed as
U14MEMS Oscillator50 MHzPS_CLK
U5MEMS Oscillator25 MHzEthernet PHY Clock
U7RTC (internal oscillator)32.768 KHzCLKOUT of RTC is not connected


Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2.5A for system startup is recommended.

Power Consumption

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

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Power on Sequence

The TE07028 SoM meets the recommended criteria to power up the Xilinx Zynq properly by keeping a specific sequence of enabling the on-board DC-DC converters and regulators dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.

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Voltage Monitor Circuit

The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

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Power Rails

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Power Signal

B2B

JM1 Pin

B2B

JM2 Pin

B2B

JM3 Pin

DirectionNotes
VIN1,3--InputSupply voltage from carrier board.
VCCO_1339--Input
VBATT-1-OutputRTC Supply voltage
3.3V19425,57OutputInternal 3.3V voltage level.
VMIO

-

2
InputVariable and supplied by carrier

1.8V

-5-OutputInternal 1.8V voltage level.


Bank Voltages

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Bank          

Schematic Name

Voltage

I/O TypeNotes
500VCCO_MIO0_5003.3VMIO
501

VCCO_MIO1_501

2.5V or 3.3VMIOsupplied by carrier.
502VCCO_DDR_5021.5VDDR3
13VCCO_131.8V or 3.3VHRSupplied by the carrier board. J1
333.3V3.3VHRSupplied by carrier board. J3
343.3V3.3VHR


353.3V3.3VHR

Supplied by the carrier board. J2, J3


Board to Board Connectors

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  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

    Include Page
    6 x 6 SoM LSHM B2B Connectors
    6 x 6 SoM LSHM B2B Connectors

Include Page
6 x 6 SoM TEM and SEM B2B Connectors
6 x 6 SoM TEM and SEM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

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VIN supply voltage-0.365VTPS54260-Q1 datasheets.
VMIO-0.53.6VPS MIO I/O supply voltage
VCCO-0.53.6VPL supply voltage for HR I/O banks
Storage Temperature-40+85°C


Recommended Operating Conditionse

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titleRecommended operating conditions

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SymbolMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
VMIO1.713.465VSee Xilinx DS187 data sheet.
VCCO1.143.465VSee Xilinx DS187 datasheet.
Operating Temperature-40+105°C


Physical Dimensions

  • Module size: 60 mm × 60 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 7 mm.

  • PCB thickness: 1.6 mm.

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titlePhysical Dimension


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Currently Offered Variants 

Power-On Sequence

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titlePower Sequency
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Create DrawIO object here: Attention if you copy from other page, objects are only linked.

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Voltage Monitor Circuit

Power Rails

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B2B Connector

JM1 Pin

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B2B Connector

JM2 Pin

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B2B Connector

JM3 Pin

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1.8

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Bank Voltages

Board to Board Connectors

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Technical Specifications

Absolute Maximum Ratings

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titleModule absolute maximum ratings.

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Recommended Operating Conditions

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titleRecommended Operating Conditions.

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Physical Dimensions

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titlePhysical dimensions drawing

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titleTrenz Electronic Shop Overview

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Trenz shop TE0xxx TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

Product changes can be seen in PCN page.

Hardware Revision Number
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DateRevisionNotePCNDocumentation Link
-01Prototypes--
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Changes

 2016-08-18

04
  • U1 DDR3 IC changed from NT5CB256M16CP-DIH to NT5CC256M16CP-DIH
  • Net DDR3-ODT0: added series resistor R55
  • Added Traceability pad
  • Net PS-POR-B: added pull-down resistor R56
 2015-12-0103
  • ...
2015-06-1202
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2015-03-0301
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Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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change list
  • smale style update

2019-05-16v. 367Pedram Babakhani
  • initial release

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