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On-board PeripheralB2BMPSoC Unit /
SoM peripheral
DescriptionTRM Section
FMC HPC J5, 24 LVDS pairs (48 I/O's)J1PL Bank (FMC_VADJ)

PL I/O-bank pins, differential pairs

FMC HPC Connector
FMC HPC J5, GTH InterfaceJ1MGT Bank10 MGT LanesFMC HPC Connector
SFP+ 2x1 Cage J14J1MGT Bank2 MGT Lanes to dual SFP+ ConnectorMGT Interfaces SFP+ and FireFly
SMA Coax J33J1On-module PLLSMA Coaxial Connector to on-module
PLL Clock Input pin
Programmable PLL Clock Generator
FMC HPC J5
  • 10 LVDS pairs (20 I/O's)
  • 1 LVDS Clock to PL Bank
  • 2 MGT Clocks to MGT Banks
J2

PL Bank (FMC_VADJ)

MGT Bank

PL I/O-bank pins, differential pairs

1 clock capable PL bank pin-pair

2 MGT clock input pin-pairs

FMC HPC Connector 
Programmable PLL Clock Generator

24-bit Audio Codec U3J3PL Bank (1.8 V)PL I/O-bank pins to on-board
24-bit Audio Codec
Intel-PC Compatible Headers and FAN Connectors
24-bit Audio Codec
10 I/O's to SC CPLD U17J3PL Bank (1.8 V)

PL I/O-bank pins to on-board
System Controller CPLD U17

System Controller CPDLsCPLDs
8 I/O's to SC CPLD U39J3PL Bank (1.8 V)

PL I/O-bank pins to on-board
System Controller CPLD U39

System Controller CPDLsCPLDs
SDIO Interface, SD- / MMC-Card MuxJ3PS MIOSDIO interface connected to
SD- / MMC-Card socket
MIO Bank Interfaces
SDIO Port Expander
Board Peripheral's I²C Interfaces
muxed to MPSoC I²C
J3PS MIOMPSoC I²C interface configured as
master connected to on-board slaves
MIO Bank Interfaces 
8-Channel I²C Switches
4 MIO to SC CPLD U17J3PS MIOFunctionality depending on MPSoC and
CPLD firmware
System Controller CPDLsCPLDs
15 MIO to SC CPLD U39J3PS MIO

Functionality depending on MPSoC and
CPLD firmware

System Controller CPDLs
Ethernet PHY RGMIIJ3PS MIOEthernet PHY U12 connected per RGMII

MIO Bank Interfaces
Gigabit Ethernet PHY

eMMC FlashJ3PS MIOeMMC Flash memory interface on PS bankMIO Bank Interfaces 
eMMC Memory
USB2.0 PHY ULPIJ2PS MIOUSB2.0 PHY U9 connected per ULPIMIO Bank Interfaces
High-speed USB ULPI PHY
SAMTEC FireFly Connector J6/J15J2MGT BankMGT Lanes to Samtec FireFly connectorMGT Interfaces SFP+ and FireFly
JTAG Interface via XMOD Header J12J2PS ConfigMPSoC USB programmable JTAG interface

MIO Bank Interfaces
JTAG Interface

USB3.0 LaneJ2PSGTUSB3.0 PS MGT Lane

MIO Bank Interfaces
PS GT Bank Interfaces

4-port USB3.0 Hub--USB3.0 (2.0 compatible) Hub with 4 portsMIO Bank Interfaces
4-port USB3.0 Hub
USB3.0 / RJ45 GbE Connector J7,
USB3.0 Connector J8
--2-port USB3.0 / RJ45 GbE Connector (stacked)MIO Bank Interfaces
25 SoM Control Signals to
SC CPLDs U17 / U39
J2On-module DC-DC
converter, PLL clock
generator
Control Signals, e.g.  "Enable"- / "Power Good"-
signals of DC-DC-converter and further on-module
peripherals

Power-On Sequence Diagram
Programmable PLL Clock Generator

150 MHz Osci Clock InputJ2-150 MHz SATA interface MGT clockOscillators

Signals DONE, INIT_B, SRST_B, ...
to SC CPLD U39

J2PS ConfigMPSoC control signal for PS- / PL configurationSystem Controller CPDLsCPLDs

SATA Connector J31
PCIe Connector J1
DisplayPort J13

J2PSGTConnectors of the MGT based data interfacesPS GT Bank Interfaces

PLL Clock Output to

  • PCIe Interface
  • On-board PLL U35
  • MGT Bank (B2B J3)
J2On-module PLL
clock generator

Reference clock signals of the on-module
programmable PLL clock generator

Programmable PLL Clock Generator
4 I/O's to PMOD P2 via IC U33J4PL Bank (FMC_VADJ)PL user I/O's accessible on PMOD connector P2CAN FD Interface and PMOD Connectors
3 I/O's to SC CPLD U17 via IC U32J4PL Bank (FMC_VADJ)PL user I/O's routed to System Controller
CPLD U17
System Controller CPDLsCPLDs
FMC HPC J5
  • 46 LVDS pairs (92 I/O's)
  • 1 LVDS Clock to PL Bank
J4PL Bank (FMC_VADJ)

PL I/O-bank pins, differential pairs

1 clock capable PL bank pin-pair

FMC HPC Connector
Programmable PLL Clock Generator

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I²C Slave Devices connected to MPSoC I²C InterfaceI²C
Switch
Position
I²C Slave AddressSchematic Names of I²C Bus Lines
8-channel I²C switch U16-0x73I2C_SDA / I2C_SCL
8-channel I²C switch U27-0x77I2C_SDA / I2C_SCL
SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL)-User programmableI2C_SDA / I2C_SCL
I²C Slave Devices connected to 8-channel I²C Switch U16I²C
Switch
Position
I²C Slave AddressSchematic Names of I²C Bus Lines
On-board Quad programmable PLL clock generator U35 Si533800x70MCLK_SDA / MCLK_SCL
8-bit I²C IO Expander U4410x26SFP_SDA / SFP_SCL
PCIe Connector J12module dependentPCIE_SDA / PCIE_SCL
SFP+ Connector J14A3module dependentSFP1_SDA / SFP1_SCL
SFP+ Connector J14B4module dependentSFP2_SDA / SFP2_SCL
Configuration EEPROM U24U4250x54MEM_SDA / MEM_SCL
Configuration EEPROM U3650x52MEM_SDA / MEM_SCL
Configuration EEPROM U4150x51MEM_SDA / MEM_SCL
Configuration EEPROM U2250x50MEM_SDA / MEM_SCL
8-bit I²C IO Expander U3850x27MEM_SDA / MEM_SCL
FMC Connector J56module dependentFMC_SDA / FMC_SCL
USB3.0 Hub configuration EEPROM U570x51USBH_SDA / USBH_SCL
USB3.0 Hub70x60USBH_SDA / USBH_SCL
I²C Slave Devices connected to 8-channel I²C Switch U27I²C
Switch
Position
I²C Slave AddressSchematic Names of I²C Bus Lines
PMOD Connector P10module dependentPMOD_SDA / PMOD_SCL
24-bit Audio Codec U310x38A_I2C_SDA / A_I2C_SCL
FireFly Connector J152module dependentFFA_SDA / FFA_SCL
FireFly Connector J223module dependentFFB_SDA / FFB_SCL
On-module Quad programmable PLL clock generator Si5345 (TE0808)40x69PLL_SDA / PLL_SCL
SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL)5User programmableSC_SDA / SC_SCL
8-bit I²C IO Expander U3460x24FF_E_SDA / FF_E_SCL
PMOD Connector P37module dependentEXT_SDA / EXT_SCL

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EEPROM ModellSchematic DesignatorMemory DensityPurpose
24LC128-I/STU24U30128 Kbituser
24AA025E48T-I/OTU362 Kbituser
24AA025E48T-I/OTU412 Kbituser
24AA025E48T-I/OTU422 Kbituser
24LC128-I/STU5128 KbitUSB3.0 Hub U4 configuration memory

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 Date

Revision

ContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • correction typ U25 CLK
  • System Controller links fixed
2019-09-03v.93John Hartfiel
  • update links
96Thomas Steffens
  • correction EEPROM Designator
  • correction typ U25 CLK

2018-07-02

v.89Martin Rohrmüller
  • Typo

2018-05-31

May 2018

v.88

John Hartfiel
  • Typo correction Table 13
  • Typo correction Table 9
2017-11-15v.86Ali Naseri
  • DIP-switches section revised and updated

2017-11-13

v.82

Ali Naseri
  • updated B2B connector max. current rating
    per pin

2017-11-13

v.80

John Hartfiel
  • rework B2B section
2017-10-19

v.79

Ali Naseri
  • added additionally MGT lanes information

2017-10-18

v.75
Ali Naseri
  • added Power Rails section

2017-08-29

v.70



John Hartfiel
  • update document change history
  • published
2017-08-28v.69Ali Naseri
  • Initial document

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all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

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Table 36: Document change history.

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