Page History
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- Kintex-7 FPGA (Kintex-7)
- EN63A0QI Voltage Regulator 1.0V (Slave)
- EN63A0QI Voltage Regulator 1.0V (Master)
- programmable PLL-clock generator (Si5338)
- B2B connector JM1 (0,50 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- B2B connector JM2 JM3 (0,50 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- B2B connector JM3 JM2 (0,50 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- System Controller CPLD (Lattice LCMXO2-256HC): 256 Macrocell CPLD
- 32 Mbyte Quad SPI Flash memory
- EP53F8QI Voltage Regulator 1.8V
- EP53F8QI Voltage Regulator 1.0V MGTAVCC
- EP53F8QI Voltage Regulator 1.2V MGTAVTT
- TPS27082L load switch for 3.3V voltage level
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| Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
|---|---|---|---|---|---|
0 | HR | - | - | 3.3V | Configuration bank |
12 | HR | JM2 | 50 I/O-pins 24 LVDS-pairs possible | User | HR-Banks support voltages from 1.2V to 3.3V standards. NOTE: BANK 12 IS NOT AVAILABLE ON THE K70T DEVICE. |
13 | HR | JM1 | 48 I/O-pins 24 LVDS-pairs possible | User | HR-Banks support voltages from 1.2V to 3.3V standards. |
14 | HR | JM1, JM3 | 8 I/O-pins, 4 I/O-pins (2 LVDS-pairs possible) | 3.3V | pins at B2B connector JM1, 3.3V IO-voltage. |
15 | HR | JM2 | 18 I/O-pins 9 LVDS-pairs possible | User | HR-Banks support voltages from 1.2V to 3.3V standards. |
16 | HR | JM1JM3 | 16 I/O-pins 8 LVDS-pairs possible | User | HR-Banks support voltages from 1.2V to 3.3V standards. |
32 | HP | NC | - | - | Bank not used. |
33 | HP | NC | - | - | Bank not used. |
| 34 | HP | NC | - | - | Bank not used. |
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| Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-01-12 | John Hartfiel | Correction: B2B and FPGA Bank location | |
| 2016-12-14 |
19 | Ali Naseri | TRM revision |
| 2013-12-02 | 0.1 | initial version |
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