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Figure 4: GTX Transceiver block diagram.
System Controller CPLD
The system controller is used to coordinate the configuration of the FPGA. The FPGA is held in reset (by driving the PROG_B signal) until the power supplies have sequenced. Setting input signal RESIN low will also reset the FPGA. This signal can be driven from the user’s PCB via the board connector.
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Technical Specifications
Absolute Maximum Ratings
| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
VIN supply voltage | -0.3 | 6.5 | V | - |
| 3.3VIN supply voltage | -0.1 | 3.6 | V | - |
| PL IO bank supply voltage for HR I/O Banks (VCCO) | -0.5 | 3.6 | V | - |
| I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - |
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | Xilinx datasheet DS182 |
| Voltage on module JTAG pins | -0.5 | VCCO_0+0.45 | V | VCCO_0 is 3.3V nominal. |
| Storage temperature | -55 | +125 | °C | - |
Table 12: Absolute maximum ratings.
Recommended
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Operating Conditions
| Parameter | Min | Max | Units | Notes | Reference Document |
|---|---|---|---|---|---|
| VIN supply voltage | 2.4 | 5.5 | V | - | EP53F8QI data sheet |
| 3.3VIN supply voltage | 3.135 | 3.465 | V | 3,3V ± 5% | - |
| PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | - | Xilinx datasheet DS182 |
| I/O input voltage for HR I/O Banks | -0.20 | VCCO+0.2 | V | - | Xilinx datasheet DS182 |
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | (*) | (*) | - | - | * check datasheet DS182 |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | - | - |
Table 13: Recommended operation conditions.
| Note |
|---|
| Please check Check Xilinx datasheet (DS182) for complete list of absolute maximum and recommended operating ratings. |
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The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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- Module size: 50 mm × 40 mm
- Mating height with standard connectors: 8mm
- PCB thickness: 1.6mm
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Overview
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