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| Note |
|---|
SPI Flash QE (Quad Enable) bit must be set, or the FPGA would not configure itself from Flash. This bit is always set at the manufacturing. |
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GTX Transceivers
The Kintex-7 device that is used on the TE0741 board has 8 GTX transceivers. All 8 are wired directly to connectors JM1 and JM3. There are also 4 clocks that are associated with the transceivers. Two of the clocks are connected directly to JM3, whilst the other two are derived from the clock generator. As there is no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.
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Figure 4: GTX Transceiver block diagram.
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System Controller CPLD
The system controller is used to coordinate the configuration of the FPGA. The FPGA is held in reset (by driving the PROG_B signal) until the power supplies have sequenced. Setting input signal RESIN low will also reset the FPGA. This signal can be driven from the user’s PCB via the board connector.
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Recommended Operating Conditions
| Parameter | Min | Max | Units | Notes | Reference Document |
|---|---|---|---|---|---|
| VIN supply voltage | 2.4 | 5.5 |
| V | - | EP53F8QI data sheet |
| 3.3VIN supply voltage | 3.135 | 3.465 |
| V | 3,3V ± 5% | - |
| PL I/O bank supply voltage for HR |
| I/O banks (VCCO) | 1.14 | 3.465 |
| V | - | Xilinx datasheet DS182 |
| I/O input voltage for HR I/O Banks | -0.20 | VCCO+0.2 |
| V | - | Xilinx datasheet DS182 | |||
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | (*) | (*) | - | - | * See datasheet DS182 |
| Voltage on Module JTAG pins | 3.135 |
| 3.465 |
| V | - | - |
Table 13: Recommended operation conditions.
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| Date | Revision | Contributors | Description | |
|---|---|---|---|---|
| 2017-01-12 | John Hartfiel | Correction: B2B and FPGA Bank location | ||
| 2016-12-14 | 19 | TRM revision | ||
| 2013-12-02 | 0.1 | Initial version |
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