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The purpose of the jumpers and the DIP-switch S4 of the Carrier Board will be explained in the following sections.
Configuring VCCIO-Voltage as example
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with mounted 4x5 SoM TE0720
The Zynq-module power supply is fixed to 5V!
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There are two base board supply-voltages VIOTA, VIOTB and for the 4x5 SoM's PL IO-banks. The supply-voltages have following pin assignments on B2B-connectors:
base-board VCCIO | base-board B2B connector-pins | standard assignment of PL IO-bank supply-voltages on TE 4x5 modules B2B connectors | base-board voltages and signals connected with |
|---|---|---|---|
| VIOTA | JB2-2, JB2-4, JB2-6 | VCCIOB (JM2-1, JM2-3) / VCCIOC (JM2-5) | HDMI_SCL, HDMI_SDA, HDMI_INT, J5 VCCIO |
| VIOTB | JB1-10, JB1-12, JB2-8, JB2-10 | VCCIOA (JM1-9, JM1-11) / VCCIOD (JM2-7, JM2-9) | VCCIO1 (Systm-Controller-CPLD pin 55, 73) |
The corresponding PL IO-bank supply-voltages of the 4x5 SoM to the selectable base-board voltages VIOTA and VIOTB are depending on the mounted 4x5 SoM and varying in order of the used model.
Refer to the SoM's schematic to get information about the specific pin assignments on B2B-connectors regarding the PL IO-bank supply-voltages and to the 4x5 Module Integration Guide for VCCIO voltage options.
Following table gives the conjunction between the B2B-connector pin assignments regarding the supply voltages of base-board supply-voltages VIOTA, VIOTB and the PL IO-banks bank's voltages of 4x5 SoMs.:
supported 4x5 SoMs vs base-board VCCIO | TE0710 | TE0711 | TE0712 | TE0713 | TE0715-xx-15 | TE0715-xx-30 | TE0720 | TE0741 | TE0841 |
|---|---|---|---|---|---|---|---|---|---|
| VIOTA | NC | B34 (VCCIOB) | B13 (VCCIOB) | - | B34 (VCCIOC) | B34 (HP bank, VCCIOC) | B33 (VCCIOC) B34 (VCCIOB) | B15 (VCCIOC) B16 (VCCIOB) | B66 (HP bank, VCCIOB) B68 (HP bank, VCCIOC) |
| VIOTB | B15 (VCCIOA) B34 (VCCIOD) | B15 (VCCIOA) B35 (VCCIOD) | B16 (VCCIOA) B15 (VCCIOD) | - | B13 (VCCIOA) B35 (VCCIOD) | B13 (VCCIOA) B35 (HP bank, VCCIOD) | B35 (VCCIOA) B13 (VCCIOD) | B13 (VCCIOA) B12 (VCCIOD) | B64 (VCCIOA) B67 (HP bank, VCCIOD) |
T
Following table describes how to configure the base-board supply-voltages by jumpers:
base-board supply-voltages vs voltage-levels | VIOTA | VIOTB | USB-VBUS | 12V0_CL | ||
|---|---|---|---|---|---|---|
| 3V3 | J17:1-2, 3 & J16: open | J17: 1-2, 3 & J16: open & J21:1-2, 3 | - | - | ||
| 2V5 | J17:1, 2-3 & J16: open | J17:1, 2-3 & J16: open & J21: 1-2, 3 | - | - | ||
| FMC-VADJ | J17: open & J16: 1-2 | J21:1, 2-3 | - | - | ||
| 5V0 intern | - | - | J9:1-2, 3 & J19: 1-2 (J20: 1-2: additional blocking-capacitors) | - | ||
| Vbus extern | - | - | J9: 1, 2-3 & J19: open | - | ||
| 12V_LC | - | - | - | J18: 1-2 |
Table 6: Configuration of base-board supply voltages via jumpers
Power On Reset (POR)
On the TE0701 the 5.0V and 3.3V power supply rails are generated by high performance DC-DC-converters from the external 12V supply. While the 3.3V plane supplies several on-board components (e.g., Lattice CPLD and FTDI Dual USB UART/FIFO IC), the 5V plane is mainly provided to power supply of the module to be carried (e.g., TE0720 Zynq SoC module). For the latter, however, special considerations must be taken (see TE0720 Power Supply). Therefore, the on-module system controller (SC) must be provided with information about the power-on-reset (POR) process, namely, the following control signals EN1, RESIN, and NOSEQ. And the SC provides, in turn, the status signal PGOOD down to the on-board System-Controller-CPLD.
| Signal | Description | ||
|---|---|---|---|
| EN1 | This CPLD output active-high signal is a “power on (PON)” signal that is usually HIGH (weak pull-up), except, the user push button S2 is pressed, which forces the related signal to be LOW (ground). EN1 enables (EN1=’1’) and disables (EN1=’0’) the power supplies on the carried module, respectively. | ||
| RESIN | This signal is controlled by the user push button S1 on the TE0701 and is forwarded directly to the SC, where it is latched together with the EN1 signal as well as the “all power rails OK” signal (1.0V and 1.8V for core; 1.5V and VTT for RAM, and 3.3V).
When RESIN (alias user push button S1) is not pushed and simultaneously the EN1 signal is asserted (EN='1') and all power rails are ok, the active-high Zynq power-on-reset signal PS_POR_B is asserted. | ||
| NOSEQ | This CPLD signal can be used to enable or disable the power sequencing mode. If the active-high NOSEQ signal is set to HIGH (NOSEQ='1') then the 1.0V and 1.8V power supplies on the carried module will be forced to be enabled. In normal mode (NOSEQ='0') the 3.3V power supply is turned on after the 1.0V and 1.8V supplies have stabilized (see TE0720 Power Supply). The latter is the default mode, i.e., for the NOSEQ pin of the SC the internal pull-down is activated. After booting, the NOSEQ pin can be used as general-purpose I/O pin. For example, the SC (REV 0.02) maps the Ethernet PHY LED0 to NOSEQ by default. However, this mapping can be changed by software after boot. | ||
| PGOOD | This active-high signal (with internal pull-up) is a status input to the CPLD about the current status of the power supply rails on the carried module (e.g., TE0720). It is routed to user LED3, which is switched on when the on-module power supply rails are not ok. |
Table 47: Generation of PGOOD-Signal
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