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Table of Contents

Table of Contents

Overview

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Refer to https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TE0705 for downloadable version of this manual and additional technical documentation of the product.
The Trenz Electronic TE0705 carrier board provides functionality for testing, evaluation and development purposes of The Trenz Electronic TE0705 carrier board provides functionality for testing, evaluation and development purposes of company's 4 x 5 cm SoMs (System on Module). The carrier board is equipped with a broad range of various components and connectors for different configuration setups and needs. On-module functional components and multipurpose I/Os of the SoM's PL and PS logic are connected via board-to-board connectors to the carrier board components and connectors for easy user access.

See "4 x 5 cm carriers" page for more information about supported 4 x 5 cm SoMs.

Block Diagram

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Figure 1: TE0705-04 Block Diagram.

Main Components

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Figure 2: 4 x 5 SoM carrier board TE0705-04.


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Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.

Block Diagram

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Figure 1: TE0705-04 Block Diagram.

Main Components

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Figure 2: 4 x 5 SoM carrier board TE0705-04. 


  1. ARM JTAG Connector (DS-5 D-Stream) J15 - PJTAG to EMIO multiplexing neededfunctionality depends on connected module
  2. 12-pin IDC Molex 90130-3212 header socket J1 (right angle, max. VCCIO voltage 3.3V)

  3. RJ45 GbE Connector

  4. SD Card Socket - Zynq SDIO0 bootable SD port
  5. 12-pin IDC Molex 90130-3212 header socket (right angle)  J2J2
  6. Micro USB Connector J12 (Device, Host or OTG Modes)
  7. Battery holder for CR1220 (RTC backup voltage)
  8. 12-pin IDC Molex 90130-1212 header socket (vertical)  J5J5
  9. 12-pin IDC Molex 90130-1212 header socket (vertical)  J6J6
  10. User Push-Button S2 ("RESTART" button by default)
  11. User Push-Button S1 ("RESET" button by default)
  12. User LEDs D6, D7, D8, D9
  13. User LEDs D4, D5, D14, D15
  14. Mini USB Connector (USB JTAG and UART Interface) J7
  15. User 4-bit DIP-Switch S3
  16. User 4-bit DIP-Switch S4
  17. FTDI FT2232H USB 2.0 High Speed to UART/FIFO
  18. Lattice Semiconductor MachXO2 1200HC System Controller CPLD
  19. Jumper J4 to fix user button S2 to switched state
  20. 40-Pin-Header J13 for access to PL IO-bank-pins
  21. 40-Pin-Header J11 for access to PL IO-bank-pins
  22. Samtec Razor Beam™ LSHM-150 B2B connector JB1
  23. Samtec Razor Beam™ LSHM-150 B2B connector JB2
  24. Samtec Razor Beam™ LSHM-130 B2B connector JB3
  25. Barrel jack Mini-Fit JR Header 2Pol for 12V power supply J10
  26. Jumper J21 to select supply voltage of VIOTB
  27. Jumper J9, J19, J20 to select supply voltage of USB-VBUS

...

  • Overvoltage, undervoltage and reverse supply protection controller
  • Barrel jack Mini-Fit JR Header 2Pol for 12V power supply
  • On-board System Controller CPLD (Lattice MachXO2 1200HC), programmable via Mini-USB JTAG interface J7
  • SoM can be programmed via ARM JTAG interface connector (J15) or programmed  through System Controller CPLD via Mini-USB JTAG interface J7
  • RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs
  • 2 x 40-pin headers J11 and J13 for access to module's PL IO bank pins
  • USB JTAG/UART interface (FTDI FT2232H) with Mini-USB connector J7
  • 8 x user LEDs (red) routed to System Controller CPLD
  • 2 x user-push buttons routed to System Controller CPLD. By default (depending on CPLD firmware) configured as system "RESET" and "RESTART" buttons
  • 2 x 4-bit DIP-switch for baseboard configuration
  • 2 x 12-pin IDC header socket (vertical) J5, J6 for accessing module's PL IO bank pins, can be used as LVDS pairs
  • 2 x 12-pin IDC header socket (right angle) J1 and J2 for accessing module's PL IO bank pins or PS MIO0 bank pins (if used with Zynq module)
  • 2 x 50-pin IDC header J11, J13 for accessing module's PL IO bank pins
  • Micro SD card socket with card detect switch, can be used for system booting
  • Micro-USB interface (J12) connected to SoM's USB transceiver (Device, Host or OTG modes)
  • Trenz Electronic 4 x 5 cm module connectors (3 x Samtec LSHM series)

...

An exception here is the 'MIO12'-pin, which is buffered with a Schmitt-Trigger buffer with a hysteresis of 5.0V.

Warning

'MIO12'-pin, is buffered with a Schmitt-Trigger buffer with a hysteresis of 5.0V.


IDC header socket J2

12-pin header J2 provides access to SoM's PL IO-bank pins routed to B2B-connector JB3. Operable with fixed (3.3V) or adjustable VCCIO voltage VIOTB (Single ended IOs, not usable as LVDS pairs).

...

The PL IO-bank supply voltage FMC_VADJ is available after the output of the 5.0V DC-DC converter is active and the EN_FMC pin of the System Controller CPLD is asserted.
 


Figure 3: Power-On sequence diagram.

...

With jumper J21, user can select between two different power sources for SoM PL IO banks supply voltage VIOTB. If set to position 1-2, fixed 3.3V is selected as VIOTB source. If set to position 2-3, FMC_VADJ is selected as VIOTB source. Voltage level of FMC_VADJ depends on the settings of DIP-switch S3, see table below:

...


J21 Position

S3-1 (CM1)

S3-2 (CM0)

FMC_VADJ

Voltage

VIOTB VoltageNotes
1-2---3.3V 
2-3

OFF

OFF

1.8V

1.8V 
2-3

ON

OFFON

2.5V

2.5V 
2-3

OFF

ONOFF

3.3V

3.3V 
2-3

ON

ON

1.8V

1.8V

This setting also enables JTAG access to the System Controller CPLD on the SoM via B2B connector JB2.

Table 3: Jumper J21 and DIP-switch S3 settings for VIOTB voltage configuration.

Note: Exact function of the S3-1 and S3-2 switches depend on the TE0705 System Controller CPLD firmware. For more detailed information, refer to the documentation of the TE0705 System Controller CPLD.

...

Table 5: Configuration of baseboard supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2, 3' means pins 1 and 2 are connected, 3 is open. 'Jx: 1, 2-3' means pins 2 and 3 are connected, 1 is open.

Note

Take care of the VCCO voltage ranges of the  particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.

It is recommended to set and measure the PL IO-bank supply

It is recommended to set and measure the PL IO-bank supply

-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM.

Technical Specifications

Absolute Maximum Ratings

Board to Board Connectors

Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

ParameterParameterMinMaxUnitsNotes

VIN supply voltage

11.4

12.6

V

12.0V supply voltage ± 5%

Storage temperature

-55125

°C

Lattice MachX02 family data sheet

...

 All dimensions are given in millimeters.

Figure 4: Physical dimensions of the TE0705-04 carrier board.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

Approximately 110 g - Plain board.

Revision History

Hardware Revision History

...

Notes

...

Figure 4: Physical dimensions of the TE0705-04 carrier board.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

Approximately 110 g - Plain board.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation link
2016-10-0404--TE0705-04

Figure 5: Hardware revision number.

Hardware revision number is printed on the PCB board next to the model number separated by the dash.

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Document Change History

DateRevisionContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
prefixv.
typeFlat
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infoTypeModified by
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  • correction J10 description
2020-08-19v.18John Hartfiel
  • correction J15 description
2019-06-27v.17John Hartfiel
  • typo VADJ DIP settings
2019-03-14v.16John Hartfiel
  •  Add B2B section
  • Note MIO12
2017-02-08

V.11

Figure 5: Hardware revision number.

Hardware revision number is printed on the PCB board next to the model number separated by the dash.

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Document Change History

DateRevisionContributorsDescription
2017-02-09

Ali Naseri, Jan Kumann TRM
  • TRM for TE0705-04
--all

Page info
infoTypeModified users
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showVersionsfalse

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Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices