Page History
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- ARM JTAG Connector (DS-5 D-Stream) J15 - PJTAG to EMIO multiplexing neededfunctionality depends on connected module
- 12-pin IDC Molex 90130-3212 header socket J1 (right angle, max. VCCIO voltage 3.3V)
RJ45 GbE Connector
- SD Card Socket - Zynq SDIO0 bootable SD port
- 12-pin IDC Molex 90130-3212 header socket (right angle) J2J2
- Micro USB Connector J12 (Device, Host or OTG Modes)
- Battery holder for CR1220 (RTC backup voltage)
- 12-pin IDC Molex 90130-1212 header socket (vertical) J5J5
- 12-pin IDC Molex 90130-1212 header socket (vertical) J6J6
- User Push-Button S2 ("RESTART" button by default)
- User Push-Button S1 ("RESET" button by default)
- User LEDs D6, D7, D8, D9
- User LEDs D4, D5, D14, D15
- Mini USB Connector (USB JTAG and UART Interface) J7
- User 4-bit DIP-Switch S3
- User 4-bit DIP-Switch S4
- FTDI FT2232H USB 2.0 High Speed to UART/FIFO
- Lattice Semiconductor MachXO2 1200HC System Controller CPLD
- Jumper J4 to fix user button S2 to switched state
- 40-Pin-Header J13 for access to PL IO-bank-pins
- 40-Pin-Header J11 for access to PL IO-bank-pins
- Samtec Razor Beam™ LSHM-150 B2B connector JB1
- Samtec Razor Beam™ LSHM-150 B2B connector JB2
- Samtec Razor Beam™ LSHM-130 B2B connector JB3
- Barrel jack Mini-Fit JR Header 2Pol for 12V power supply J10
- Jumper J21 to select supply voltage of VIOTB
- Jumper J9, J19, J20 to select supply voltage of USB-VBUS
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- Overvoltage, undervoltage and reverse supply protection controller
- Barrel jack Mini-Fit JR Header 2Pol for 12V power supply
- On-board System Controller CPLD (Lattice MachXO2 1200HC), programmable via Mini-USB JTAG interface J7
- SoM can be programmed via ARM JTAG interface connector (J15) or programmed through System Controller CPLD via Mini-USB JTAG interface J7
- RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs
- 2 x 40-pin headers J11 and J13 for access to module's PL IO bank pins
- USB JTAG/UART interface (FTDI FT2232H) with Mini-USB connector J7
- 8 x user LEDs (red) routed to System Controller CPLD
- 2 x user-push buttons routed to System Controller CPLD. By default (depending on CPLD firmware) configured as system "RESET" and "RESTART" buttons
- 2 x 4-bit DIP-switch for baseboard configuration
- 2 x 12-pin IDC header socket (vertical) J5, J6 for accessing module's PL IO bank pins, can be used as LVDS pairs
- 2 x 12-pin IDC header socket (right angle) J1 and J2 for accessing module's PL IO bank pins or PS MIO0 bank pins (if used with Zynq module)
- 2 x 50-pin IDC header J11, J13 for accessing module's PL IO bank pins
- Micro SD card socket with card detect switch, can be used for system booting
- Micro-USB interface (J12) connected to SoM's USB transceiver (Device, Host or OTG modes)
- Trenz Electronic 4 x 5 cm module connectors (3 x Samtec LSHM series)
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An exception here is the 'MIO12'-pin, which is buffered with a Schmitt-Trigger buffer with a hysteresis of 5.0V.
Warning |
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'MIO12'-pin, is buffered with a Schmitt-Trigger buffer with a hysteresis of 5.0V. |
IDC IDC header socket J2
12-pin header J2 provides access to SoM's PL IO-bank pins routed to B2B-connector JB3. Operable with fixed (3.3V) or adjustable VCCIO voltage VIOTB (Single ended IOs, not usable as LVDS pairs).
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J21 Position | S3-1 (CM1) | S3-2 (CM0) | FMC_VADJ Voltage | VIOTB Voltage | Notes |
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1-2 | - | - | - | 3.3V | |
2-3 | OFF | OFF | 1.8V | 1.8V | |
2-3 | ON | OFFON | 2.5V | 2.5V | |
2-3 | OFF | ONOFF | 3.3V | 3.3V | |
2-3 | ON | ON | 1.8V | 1.8V | This setting also enables JTAG access to the System Controller CPLD on the SoM via B2B connector JB2. |
Table 3: Jumper J21 and DIP-switch S3 settings for VIOTB voltage configuration.
Note: Exact function of the S3-1 and S3-2 switches depend on the TE0705 System Controller CPLD firmware. For more detailed information, refer to the documentation of the TE0705 System Controller CPLD.
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||||||
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| John Hartfiel |
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2020-08-19 | v.18 | John Hartfiel |
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2019-06-27 | v.17 | John Hartfiel |
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2019-03-14 | v.16 | John Hartfiel |
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2017-02-08 | V.11 | Ali Naseri, Jan Kumann |
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| 2017-02-08 | V.11 | Ali Naseri, Jan Kumann |
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Disclaimer
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