Page History

Overview

Refer to https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TE0705 for downloadable version of this manual and additional technical documentation of the product.

See "4 x 5 cm carriers" page for more information about supported 4 x 5 cm SoMs.

Block Diagram

Image Removed

Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.

Block Diagram

Image Added

Figure 1: TE0705-04 Block Figure 1: TE0705-04 Block Diagram.

Main Components

Image Modified

Figure 2: 4 x 5 SoM carrier board TE0705-04. 

1. ARM JTAG Connector (DS-5 D-Stream) J15 - PJTAG to EMIO multiplexing neededfunctionality depends on connected module
2. 12-pin IDC Molex 90130-3212 header socket J1 (right angle, max. VCCIO voltage 3.3V): mapped to 8 Zynq PS MIO0-bank-pins (MIO0, MIO9 to MIO15), 6 pins (MIO10 to MIO15) are additionally connected to TE0705 System Controller CPLD

3. RJ45 GbE Connector

5. RJ45 GbE Connector

6. SD Card Socket - Zynq SDIO0 Bootable bootable SD port
7. 12-pin IDC Molex 90130-3212 header socket (right angle)  J2 for access to Zynq-module's PL IO-bank pins (not usable as LVDS pairs, only single-ended IOs, max. VCCIO voltage: VIOTB)J2
8. Micro USB Connector J12 (Device, Micro USB Connector J12 (Device, Host or OTG Modes)
9. Battery holder for CR1220 (RTC backup voltage)
10. 12-pin IDC Molex 90130-1212 header socket (vertical)  J5 for access to Zynq-module's PL IO-bank pins (4 LVDS pairs, max. VCCIO voltage: VIOTB)J5
11. 12-pin IDC Molex 90130-1212 header socket (vertical)  J6 for access to Zynq-module's PL IO-bank pins (4 LVDS pairs, max. VCCIO voltage: VIOTB)J6
12. User Push-Button User Push-Button S2 ("RESTART" button by default)
13. User Push-Button S1 ("RESET" button by default)
14. User LEDs D6, D7, D8, D9 (function mapping depends on firmware of System Controller CPLD)
15. User LEDs D4, D5, D14, D15 (same as above)
16. Mini USB Connector (USB JTAG and UART Interface) J7
17. User 4-bit DIP-Switch S3
18. User 4-bit DIP-Switch S4
19. FTDI FT2232HQ FT2232H USB 2.0 High Speed to UART/FIFO
20. Lattice Semiconductor MachXO2 1200HC System Controller CPLD
21. Jumper J4 to fix user button S2 to switched state
22. 40-Pin-Header J13 for access to PL IO-bank-pins
23. 40-Pin-Header J11 for access to PL IO-bank-pins
24. Samtec Razor Beam™ LSHM-150 B2B connector JB1
25. Samtec Razor Beam™ LSHM-150 B2B connector JB2
26. Samtec Razor Beam™ LSHM-130 B2B connector JB3
27. Barrel jack Mini-Fit JR Header 2Pol for 12V power supply J10
28. Jumper J21 to select supply voltage of VIOTB
29. Jumper J9, J19, J20 to select supply voltage of USB-VBUS

Key Features

• Overvoltage-, undervoltage - and reversed- reverse supply -voltage- protection controller
• Mini-Fit JR Header 2Pol Barrel jack for 12V power supply
• Carrier Board On-board System Controller CPLD (Lattice MachXO2 1200HC), programable by programmable via Mini-USB JTAG -Interface J7interface J7
• SoM can be programmed  through Zynq-module programable by ARM-JTAG-Interface-Connector (J15) or by System Controller CPLD via Mini-USB JTAG -Interface interface J7
• RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs
• 2x 2 x 40-Pin-Header pin headers J11 and J13  for access to Zynq- module's PL IO - bank -pins, operable with fixed (3.3V) or adjustable IO-voltage VIOTB (not usable as LVDS pairs, only single-ended IOs)
  pins
  
• USB JTAG/UART interface (FTDI FT2232HUSB JTAG- and UART-Interface (FTDI FT2232HQ) with Mini-USB -Connector connector J7
  
• 8 x user LEDs (red) routed to System Controller CPLD, 8 x red
  
• 2 x user-push button buttons routed to System Controller CPLD; by default . By default (depending on CPLD firmware) configured as system "RESET" and "RESTART" button (depends on CPLD-Firmware)buttons
  
• 2 x 4-bit DIP-Switch switch for baseboard - configuration (3 switches routed to System Controller CPLD, 3 switches to set voltage FMC_VADJ, 1 switch routed to Zynq-module (MIO0), 1 switch enables Mini-USB JTAG-Interface J7)
  
  
• 2 x 12-pin IDC header socket (vertical) J5, J6 for access to Zynq-accessing module's LVDS pairs (max. VCCIO voltage: VIOTB) PL IO bank pins, can be used as LVDS pairs
  
• 2 x 1212-pin IDC header socket (right angle) J1 for access to Zynq-and J2 for accessing module's PL IO bank pins or PS MIO0 - bank - pins MIO0, MIO9 ... MIO15 (J1-6 (MIO12) buffered by Schmitt-Trigger-Buffer (5.0V Hysteresis), else max. VCCIO voltage 3.3V)(if used with Zynq module)
  
• 2 x 50-pin IDC header J11, J13 for accessing 12-pin IDC header socket (right angle) J2 for access to Zynq- module's PL IO - bank - pins (max. VCCIO voltage: VIOTB)
  
• Micro SD card socket with card detect switch, can be used to boot for system booting
• Micro-USB -Interface interface (J12) connected to Zynq-module SoM's USB transceiver (Device, Host or OTG modes)
• Trenz Electronic 4 x 5 cm module Socket connectors (3 x Samtec LSHM series connectors)

Interfaces and Pins

Micro SD Card Socket

Micro SD Card card socket is not directly wired connected to the B2B connector pins, but through a Texas Instruments TXS02612 SDIO Port Expander , which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq-module. The Micro SD Card . The Micro SD card has 3.3V signal voltage level , but the MIO-bank on the Xilinx Zynq-module has VCCIO while Xilinx Zynq MIO bank uses 1.8V for VCCIO.

Dual

...

Channel USB to UART/FIFO

The TE0705 Carrier Board carrier board has on-board USB 2.0 High Speed high-speed to UART/FIFO IC FT2232HQ FT2232H from FTDI. Channel A can be used as JTAG interface Interface (MPSSE) to program the System Controller CPLD, . Channel B can be used as UART interface Interface routed to CPLD. There are also 6 additionally additional bus-lanes available for user-specific use. The FT2232HQ-Chip can also be used as FIFO in FT245 asynchronous mode.

There is also a 256-byte serial There is also a standard 256 Byte EEPROM connected to the FT2232HQ-chip available to store custom configuration settings. EEPROM settings can be changed using FTDI provided tools that can be downloaded from FTDI website. See FTDI website for more informationFT2232H chip pre-programmed with license code to support Xilinx programming tools.

USB Interface

The TE0705 carrier board has two physical USB - connectors:

• J7 as mini-USB - connector wired to on-board FTDI FT2232HQ FT2232H chip.
• J12 as micro-USB - connector wired to B2B connector JB3 (usually there is usually an USB - transceiver on the SoMsSoM).

JTAG Interface

JTAG access to the on-board System Controller CPLD and Xilinx Zynq-module is SoM is provided via Minimini-USB JTAG Interface interface J7 (FTDI FT2232H) and controlled by DIP switch S3-3.The JTAG port of the CPLD is enabled by setting switch S3-3 labeled as "ENJTAG" to the OFF-position

LEDs

There are eight LEDs (D6, D7, D8, D9, D4, D5, D14, D15) available to the user. All LEDs are red colored and connected mapped to the on-board System Controller CPLD. Their functions are programmable and depend on the firmware of the System Controller CPLD. For detailed information, please refer to the documentation of the TE0705 System Controller CPLD.

One green Green LED D22 shows the is to indicate availability of the 3.3V power supply voltage of to the TE0705 Carrier Boardcarrier board.

4-bit DIP-switch S3

...

Switch	Functionality
S3-1	CM1: Mode pin 1 (routed to Carrier System Controller CPLD).
S3-2	CM0: Mode pin 0 (routed to Carrier System Controller CPLD).
S3-3	JTAGEN: Set to ON for normal JTAG operation. Must be moved to OFF position for TE0705 System Controller CPLD update only.
S3-4 MIO0: Readable signal by System Controller CPLD and mounted TE07xx Module	MIO0: Set MIO0 pin (on MIO0-Bank) on Zynq modules, else active-low user IO pin.

Table 1: Configuration of DIP-switch S3.

4-bit DIP-switch S4

Additionally , on the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (16) in Figure 1) available. The signals of the switch are routed to carrier board's System Controller CPLD and are fully user-configurable depending on a customer developed S4 available routed to the System Controller CPLD which function is user configurable via custom CPLD firmware. Please refer to the documentation of the TE0705 System Controller CPLD to get information how to put these user-switches in operation documentation for more information.

All switch S4 pins are connected to 3.3V pull-up resistors in OFF position.

User

...

Push-Buttons

On the TE0705 Carrier Board there are two push buttons (S1 and S2) and are routed to the System Controller CPLD and available to the user. The default mapping of the push buttons is as follows:

...

The functionality of the push buttons depends on the CPLD firmware. For detailed information of the function of the push buttons, please refer to the documentation of the TE0705 System Controller CPLD.

Ethernet

The TE0701 TE0705 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J14) with two LEDs.

...

PHY LEDs are not connected directly to the module's B2B connectors as the TE 4 x 5 module cm modules have no dedicated PHY LED pins assigned. PHY LEDs are connected to the TE0705 System Controller CPLD, that can route those LEDs to some the module's I/O IO Pins. In that case, the CPLD has to map the PHY LEDs to corresponding module's IO pins.

See documentation of the TE0705 System Controller CPLD to get information of the function of the PHY LEDs.

IDC header sockets J5 and J6

On the TE0705 there two IDC header available for access to SoM's PL IO-bank pins

J5 and J6 sockets signal routing is done as differential pairs for pins 1-3, 2-4, 5-7, 6-8. The differential pairs are operable with , hence 4 LVDS pairs are possible on this sockets. The differential pairs are operable with max. VCCIO voltage VIOTB.

Please use Master Pinout Table table as primary reference for the pin mapping information.

IDC header socket J1

Zynq-moduleIDC header J1 provides access to SoM's MIO0PL IO-bank pins, whereby 6 pins (net name: 'MIO10' to 'MIO15') of this header are also routed to the System Controller CPLD.

If Zynq module is mounted on the TE0705 carrier board, the pins of this header are routed to the corresponding pins of the PS logic of the SoM: MIO0-bank pins MIO0, MIO9-MIO15 are accessible on header J1 and operable with max. VCCIO voltage 3.3V.

MIO0, MIO9-MIO15 are accessible on socket J1. Maximal VCCIO voltage is 3.3V on this socket. An exception here is the 'MIO12'-pin, which is buffered with a Schmitt-Trigger -Buffer with a Hystersis buffer with a hysteresis of 5.0V.

IDC header socket J2

Zynq-module12-pin header J2 provides access to SoM's PL IO-bank pins are accessible on socket J2. The IO-signals are routed from this socket to B2B-connector JB3 and are only single-ended IOs, hence this signal-pins are . Operable with fixed (3.3V) or adjustable VCCIO voltage VIOTB (Single ended IOs, not usable as differential pairs. Maximal VCCIO voltage is VIOTB on this socketLVDS pairs).

40-pin headers J11 and J13

40-Pin-Header pin header J11 and J13  for provide access to Zynq-moduleSoM's PL IO-bank - pins on routed to B2B-connectors JB1 and JB2. Operable with fixed (3.3V) or adjustable VCCIO voltage VIOTB (Single ended IOs, not usable as LVDS pairs, only single-ended IOs).

Power and Power-On Sequence

Power Supply

Power Single 12V power supply with minimum current capability of 3A at 12V for system startup is recommendedis recommended to operate the board.

Power-On Sequence

The All on-board voltages of the carrier board will be powered up simultaneously after one when single power-supply with a nominal voltage of 12V is connected to the power-jack J10.

The PL IO-bank supply voltage FMC_VADJ will be is available after the output of the 5.0V DC-DCDC-DC converter is active and the pin EN_FMC pin of the SC-System Controller CPLD is asserted.
 

Image Modified

Figure 3: Power-Up On sequence diagram.

Configuring VCCIO 

...

The purpose of the jumper and the DIP-switch S3 of the Carrier Board will be explained in the following sections.

...

VCCIO

...

Voltage Level DIP-Switch S3

There is the possibility to select the module's PL IO-bank's supply voltage VIOTB to fixed adjustable voltages VADJ. Therefore, the jumper J21 has to be set to the position 1, 2-3, to connect the pins 'VIOTB' and 'ADJ'. On position 1-2, 3, the supply voltage VIOTB will be fixed to 3.3V

Table 3 shows the switch-configuration of the DIP-switch S3 to set the voltage VADJ.

Note: The configuration of VADJ depends on the used firmware of the System Controller CPLD. For detailed information, refer to the documentation of the TE0705 System Controller CPLD.

With jumper J21, user can select between two different power sources for SoM PL IO banks supply voltage VIOTB. If set to position 1-2, fixed 3.3V is selected as VIOTB source. If set to position 2-3, FMC_VADJ is selected as VIOTB source. Voltage level of FMC_VADJ depends on the settings of DIP-switch S3, see table below:

Configuring Power Supply of the Micro USB Connector (Device, Host or OTG Modes) 

The TE0705 carrier board can be configured as a USB host device. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro USB port on J12). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the over-current logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 100µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K (J9: 1-2, 3) or 10K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY on the mounted SoM, which is, in turn, connected to the Zynq FPGA. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (100 µF added).

Additionally, the TE0705 carrier board is equipped with a second mini USB port J7 that is connected to a "USB to multi-purpose UART/FIFO IC" from FTDI (FT2232HQFT2232H) and provides a USB-to-JTAG interface between a host PC and the TE0705 carrier board and the Zynq-modulemounted SoM, respectively. Because it acts as a USB function device, no power switch is required (and only a ESD protection must be provided) in this case.

Summary of VCCIO

...

Configuration

All B2B VCCIO supply voltages to On the TE0705 carrier board all PL IO-bank's supply voltages of the 4 x 5 SoM (VCCIOA, VCCIOB, VCCIOC and VCCIOD, VCCIOD; see 4 x 5 Module Integration Guide) are connected to the VCCIO voltage 3.3V VIOTB, which is either fixed to 3.3V (J21: 1-2, 3) or selectable with the adjustable supply-voltage FMC_VADJ (J21: 1, 2-3). The supply-voltages have following pin assignments on B2B-connectors:

...

Table 5: Configuration of baseboard supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2, 3' means pins 1 and 2 are connected, 3 is open. 'Jx: 1, 2-3' means pins 2 and 3 are connected, 1 is open., 1 is open.

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

...

Physical Dimensions

...

 All dimensions are given in millimeters.

Image Modified

Figure 4: Physical dimensions of the TE0705-04 carrier board.

...

...

Figure 5: Hardware revision number.

Hardware revision number is printed on the PCB board next to the model number separated by the dash.

Image Added

Document Change History

Hardware Revision History

Disclaimer