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The MIO-bank-pins, of the Zynq-module, which are dedicated to SDIO-interface, are also accessible by PMOD-Connector J2, which is configurable by the "SEL_SD"-signal of the System-Controller-CPLD. The connector Connector J2 has max. VCCIO-voltage 3.3V.

Dual channel USB to UART/FIFO

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See documentation of the TE0701 Sytem-Controller-CPLD to get information of the function of the PYH PHY LEDs.

Pmod Slots

J5 and J6 Pmod signal routing is done as differential pairs for pins 1-2, 3-4, 7-8, 9-10.

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