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The TE0701 carrier board can be configured as a USB host. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro USB port on J12; 13). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the overcurrent logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 100µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K (J9: 1-2, 3) or 10K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY from SMSC (USB3320) on the GigaZee modulemounted SoM, which is, in turn, connected to the Zynq FPGA. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (100 µF added).
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base-board supply-voltages | base-board B2B connector-pins | standard assignment of PL IO-bank supply-voltages on TE 4x5 module's B2B connectors | base-board voltages and signals connected with |
|---|---|---|---|
| VIOTA | JB2-2, JB2-4, JB2-6 | VCCIOB (JM2-1, JM2-3) / VCCIOC (JM2-5) | HDMI_SCL, HDMI_SDA, HDMI_INT, J5 VCCIO |
| VIOTB | JB1-10, JB1-12, JB2-8, JB2-10 | VCCIOA (JM1-9, JM1-11) / VCCIOD (JM2-7, JM2-9) | VCCIO1 (Systm-Controller-CPLD pin 55, 73) |
Table 4: base-board supply-voltages VIOTA and VIOTB
| Note |
|---|
Note: The corresponding PL IO-voltage supply voltages of the 4x5 SoM to the selectable base-board voltages VIOTA and VIOTB are depending on the mounted 4x5 SoM and varying in order of the used model. Refer to SoM's schematic to get information about the specific pin assignment on module's B2B-connectors regarding PL IO-bank supply voltages and to the 4x5 Module integration Guide for VCCIO voltage options. |
Following table gives the conjunction between the base-board supply-voltages VIOTA, VIOTB and the PL IO-bank's voltages of 4x5 SoMs:
supported 4x5 SoMs vs base-board VCCIO | TE0710 | TE0711 | TE0712 | TE0713 | TE0715-xx-15 | TE0715-xx-30 | TE0720 | TE0741 | TE0841 |
|---|---|---|---|---|---|---|---|---|---|
| VIOTA | NC | B34 (VCCIOB) | B13 (VCCIOB) | B13 (VCCIOB) | B34 (VCCIOC) | B34 (HP bank, VCCIOC) | B33 (VCCIOC) B34 (VCCIOB) | B15 (VCCIOC) B16 (VCCIOB) | B66 (HP bank, VCCIOB) B68 (HP bank, VCCIOC) |
| VIOTB | B15 (VCCIOA) B34 (VCCIOD) | B15 (VCCIOA) B35 (VCCIOD) | B16 (VCCIOA) B15 (VCCIOD) | B16 (VCCIOA) B15 (VCCIOD) | B13 (VCCIOA) B35 (VCCIOD) | B13 (VCCIOA) B35 (HP bank, VCCIOD) | B35 (VCCIOA) B13 (VCCIOD) | B13 (VCCIOA) B12 (VCCIOD) | B64 (VCCIOA) B67 (HP bank, VCCIOD) |
Table 5: base-board supply-voltages VIOTA and VIOTB in conjunction with PL IO-bank voltages
Following table describes how to configure the base-board supply-voltages by jumpers:
base-board supply-voltages vs voltage-levels | VIOTA | VIOTB | USB-VBUS | 12V0_CL |
|---|---|---|---|---|
| 3V3 | J17:1-2, 3 & J16: open | J17: 1-2, 3 & J16: open & J21:1-2, 3 | - | - |
| 2V5 | J17:1, 2-3 & J16: open | J17:1, 2-3 & J16: open & J21: 1-2, 3 | - | - |
| FMC_VADJ | J17: open & J16: 1-2 | J21:1, 2-3 | - | - |
| 5V0 intern | - | - | J9:1-2, 3 & J19: 1-2 (J20: 1-2: additional decoupling-capacitor 100 µF) | - |
| Vbus extern | - | - | J9: 1, 2-3 & J19: open | - |
| 12V_LC | - | - | - | J18: 1-2 |
Table 6: Configuration of base-board supply voltages via jumpers
| Note |
|---|
| It is recommended to set and measure the PL IO-bank supply-voltages before the installation of TE 4x5 modules, to avoid failures and damages to the functionality of the mounted SoM. |
Power On Reset (POR)
On the TE0701 the 5.0V and 3.3V power supply rails are generated by high performance DC-DC-converters from the external 12V supply. While the 3.3V plane supplies several on-board components (e.g., Lattice CPLD and FTDI Dual USB UART/FIFO IC), the 5V plane is mainly provided to power supply of the module to be carried (e.g., TE0720 Zynq SoC module). For the latter, however, special considerations must be taken (see TE0720 Power Supply). Therefore, the on-module system controller (SC) must be provided with information about the power-on-reset (POR) process, namely, the following control signals EN1, RESIN, and NOSEQ. And the SC provides, in turn, the status signal PGOOD down to the on-board System-Controller-CPLD.
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| date | revision | authors | description |
|---|---|---|---|
| 2017-01-19 | Ali Naseri | ||
| 2017-01-13 | V20 | Ali Naseri | added section for base-board supply- voltage configuration |
| 2016-11-29 | V10
| Ali Naseri | TRM update due to new revision 06 of the carrier board. |
| 2016-11-28 | V4 | Ali Naseri | TRM adjustment to the newest revision (05) of TE0701 Carrier Board. |
| 2014-02-18 | 0.2
| Sven-Ole Voigt | TE0701-03 (REV3) updated |
| 2014-01-05 | 0.1 | Sven-Ole Voigt | Initial release |
All |
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