Page History
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Name | Direction | Pin | Description |
---|---|---|---|
JTAGEN | in | 26 | Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA) |
TMS / M_TMS | IN | 29 | JTAG from B2B connector |
TCK / M_TCK | IN | 30 | JTAG from B2B connector |
TDI / M_TDI | IN | 32 | JTAG from B2B connector |
TDO / M_TDO | OUT | 1 | JTAG from B2B connector |
F_TMS / C_TMS | OUT | 21 | JTAG to FPGA |
F_TCK / C_TCK | OUT | 17 | JTAG to FPGA |
F_TDI / C_TDI | OUT | 23 | JTAG to FPGA |
F_TDO / C_TDO | IN | 20 | JTAG to FPGA |
ULI_SYSTEM / XIO | IN | 4 | FPGA access W22 PIN |
FPGA_IO | INOUT | 10 | FPGA access U22 PIN |
RESIN | IN | 16 | RESETIN from B2B connector (Negative Reset) |
DONE | IN | 28 | FPGA Configuration DONE_0 Pin |
PROG_B | OUT | 27 | FPGA Configuration PROGRAM_B_0 Pin |
PGOOD | OUT | 12 | PGOOD to B2B connector |
3.3V / PG_SENSE | IN | 25 | from module generated 3.3V Voltage |
EN1 | IN | 11 | Power Enable from B2B Connector (Positive Enable) |
SYSLED2 / LED1 | OUT | 8 | Module LED D1 (GreenRed) |
SYSLED1/ LED2 | OUT | 9 | Module LED D2 (RedGreen) |
MODE | 13 | / currently_not_used | |
NOSEQ | 14 | / currently_not_used | |
ULI_CPLD | 5 | / currently_not_used |
...
LED | STATUS | Condition | User defined |
---|---|---|---|
LED1 (Red) | ON | RSIN=0 | --- |
LED1 (Red) | Blink | RSIN=1, DONE=0 | --- |
LED1 (Red) | X | RSIN=1, DONE=1 | FPGA_IO Pin |
LED2 (Green) | ON | RSIN=0 | --- |
LED2 (Green) | Blink | RSIN=1, DONE=0 | --- |
LED2 (Green) | X | RSIN=1, DONE=1 | XIO Pin |
Appx. A: Change History and Legal Notices
...
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | |
---|---|---|---|---|---|---|
20162017-1101-1626v.15 | REV01
| REV01 | REV01, REV02 | Work in progress | ||
2016-11-04 |
v.1 | --- | Initial release | |||
All |
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