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Table of Contents

Table of Contents

Overview


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Refer to https://

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wiki.trenz-electronic.de/

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display/

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PD/TE0713+TRM for the online version of this manual and the rest of available documentation.



Trenz Electronic TE0713 is an industrial-grade FPGA module integrating Xilinx Artix-7 FPGA, USB 3.0 to FIFO bridge, 1 GByte of DDR3 DDR3L SDRAM, 32 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Block Diagram

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Main Components

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Key Features

  • Xilinx Artix-7 (15T to 200T) SoM (System on Module)series FPGA
  • Both industrial and commercial temperature ranges available
  • Rugged for high shock and high vibration resistance
  • 1 GByte DDR3 DDR3L 32-bit SDRAM
  • 32 MByte QSPI Flash memory (with XiP support)
  • USB 3.0 to FIFO interface bridge
  • Programmable clock quad generator
    • GTP transceiver clock (default 125 MHz)
    • Fabric clock (default 200 MHz)
  • Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
  • 142 152 FPGA I/Os (71 75 differential pairs) available via B2B connectors
  • 4 GTP (multi gigabit Gigabit transceiver) lanes 
  • External clock input for GTP transceivers via B2B connector
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • User configurable LED
  • Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Components

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  1. Xilinx Artix-7 XC7A series FPGA, U1
  2. 32 MByte QSPI Flash memory, U4
  3. 30.000 MHz quartz crystal, Y1
  4. System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3
  5. Green LED (SYSLED1), D1
  6. 4 Gbit DDR3L 256M x 16 SDRAM, U15
  7. Altera Enpirion 12A PowerSoC DC-DC converter, U14
  8. Silicon Labs programmable quad clock generator, U2
  9. SiTime low-power programmable oscillator @ 25.000000 MHz, U9
  10. 4 Gbit DDR3L 256M x 16 SDRAM, U19
  11. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  12. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  13. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
  14. FTDI USB 3.0 to FIFO interface bridge, U11
  15. Texas Instruments 3A step-down converter (DDR_PWR), U7
  16. Texas Instruments 3A step-down converter (1.8V), U5
  17. Texas Instruments 3A step-down converter (1.2V_MGT), U8
  18. Texas Instruments 3A step-down converter (1V_MGT), U6
  19. Texas Instruments PFET load switch, Q1

Initial Delivery State

Programmable unit

Content

Notes

Xilinx Artix-7 FPGANot programmedU1
System Controller CPLDProgrammedU3
SPI Flash OTP areaEmptyU4

SPI Flash main array

EmptyU4
SPI Flash Quad Enable bitSetU4

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13JM114VCCIO13Supplied by the baseboard.
13JM218VCCIO13Supplied by the baseboard.
13JM32VCCIO13Supplied by the baseboard.
14JM183.3V 
14JM3123.3V 
15JM248VCCIO15Supplied by the baseboard.
15JM22VCCIO15Supplied by the baseboard.
16JM148VCCIO16Supplied by the baseboard.

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JTAGEN pin in B2B connector JM1 is used to select JTAG access for FPGA or SC System Controller CPLD:

JTAGENJTAG Access To
LowArtix-7 FPGA
HighSystem Controller CPLD

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System Controller I/O Pins

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Pin NameModeFunctionDefault Configuration
PGOODOutputPower goodActive high when all on-module power supplies are working properlyPower Good Pin is zero, if RESIN, EN1, PG_SENSE or PG_DDR_PWR are low, else high impedance. EN1 is also used to enable 1V Power (connected directly outside of the CPLD).
JTAGENInputJTAG selectLow for normal operation, high for System Controller CPLD access.
EN1InputPower EnableWhen forced low, pulls PROG_B low to emulate power on reset.
RESIN

When forced low, pulls PROG POR_B low to emulate power on reset.
NOSEQ-No functionNot used.
MODE-No functionNot used.

Note: Pin functionality depends on the running CPLD Firmware, newest one is described here TE0713 CPLD

On-board LEDs

The TE0713-01 module has one LED which is connected to the System Controller CPLD. Once FPGA configuration has completed, it can be used by the user's design. 

LEDColorSC SignalSC PinNotes
D1GreenSYSLED18Exact function is defined by SC CPLD firmware.

Clocking

On-board Si5338 programmable clock generator chip is used to generate clocks with 25 MHz oscillator as input connected to the pin IN3 as input reference. There is a I2C I2C bus connected connection between the FPGA bank 14 (master) and clock generator chip (slave) which can be used to program output frequencies. See the reference design for more information.

CLK OutputFPGA BankFPGA PinIO StandardNet NameDefault FreqNote
CLK0 ------N.C.
CLK1-- ----

N.C.

CLK2216F6/E6AutoMGT_CLK0_P/N125 MHzGTP transceiver clock.
CLK335H4/G4LVDSPLL_CLK_P/N200 MHz

AC coupled, board termination

On-board Peripherals

32 MByte Quad SPI Flash Memory

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System Controller CPLD (Lattice Semiconductor MachXO2-256HC, U3) is used to control FPGA configuration process. The FPGA is held in reset (by driving the PROG_B signal low) until all power supplies have stabilized.

By driving signal RESIN to low you can reset the FPGA. This signal can be driven from the user’s baseboard PCB via the B2B connector JM2 pin 18.

Input EN1 is also gated to FPGA reset, should be open or pulled up for normal operation. By driving EN1 low, on-board DC-DC converters will be not turned off.

User can create their own System Controller design using Lattice Diamond software. Once created it can be programmed into CPLD via JTAG interface.

CPLD Firmware description:

DDR3L

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SDRAM

The TE0713-01 SoM has two 4 Gbit volatile DDR3 SDRAM ICs (U15 and U19) for storing user application code and data.

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TE0713-01 is equipped with the FTDI FT600Q high performance USB 3.0-to-FIFO interface bridge chip.

FTDI doesn't support 245 Synchronous FIFO mode on TE0713, please use FT60X Chip Configuration Programmer to change Mode into  “Multi-Channel FIFO mode”.

Info
SSTX_P and SSTX_N ar swapped on the PCB,this will be corrected automatically on link training on USB3


Power and Power-On Sequence

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See Xilinx datasheet DS181 - "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0713 module.

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Power Rails

Power Rail Name

B2B Connector JM1 Pin

B2B Connector JM2 Pin

Direction

Notes

VIN

1, 3, 52, 4, 6, 8InputSoM supply voltage (from the baseboard).
3.3VIN13, 15-InputSoM supply voltage (from the baseboard).
DDR_PWR-19OutputModule internal supply of 1.35V level.
1V---Module internal supply of 1V level.
1V_MGT---Module internal supply of 1V for bank 216 transceivers.
1.2V_MGT---Module internal supply of 1.2V for bank 216 transceivers.

1.8V

39-Output

Module internal 1.8V level. Maximum 300mA available.

3.3V-10, 12OutputModule internal 3.3V level.
VCCIO13-1, 3Input

High-Range bank supply voltage (from the baseboard).

VCCIO15-7, 9InputHigh-Range bank supply voltage (from the baseboard).
VCCIO169, 11-InputHigh-Range bank supply voltage (from the baseboard).
VREF_JTAG-91OutputJTAG reference voltage (3.3V).

Board to Board Connectors

Include Page
IN:Samtec LSHMIN:Samtec LSHM
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B Connectors

Variants Currently In Production

Module Variant

FPGA

Junction Temperature

Temperature Range
TE0713-01-100-2CXC7A100T-2FGG484C0°C to 85°CCommercial grade
TE0713-01-200-2CXC7A200T-2FBG484C0°C to 85°CCommercial grade

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

  
-0.37.0

V

 
See EN63A0QI and TPS82085 datasheets.
3.3VIN supply voltage
  V Storage temperature (ambient)
-0.53.75VSee LCMXO2-256HC datasheet.
HR I/O banks supply voltage (VCCO)-0.53.6
VXilinx datasheet DS181
HR I/O banks input voltage-0.4VCCO + 0.55VXilinx datasheet DS181
GTP transceivers Tx/Rx input voltage-0.51.26VXilinx datasheet DS181

Storage temperature

-55

100

°C

See IM4G16D3FABG
See IM4G16D3FABG datasheet.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage
  
2.56.0V
 
See TPS82085 datasheet.
3.3VIN supply voltage2.3753.6VSee LCMXO2-256HC datasheet.
HR I/O banks supply voltage
  V 
(VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.2VXilinx datasheet DS181

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Note
Assembly variants for higher storage temperature range are available on request.

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Physical Dimensions

  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.
  • Mating height with standard connectors: 8mm
  • PCB thickness: 1.6mm
  • Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters.

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Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

 Image Added Image Added

Weight

21 g Plain module.

8.8 g Set of nuts and bolts.

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DateRevision

Notes

PCNDocumentation Link
2016-06-30

01

First production revision


TE0713-01


Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History

Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
prefixv.
typeFlat



Page info
infoTypeModified by
typeFlat

  • Note USB3
2019-07-03v.13John Hartfiel
  • History bugfix
  • Correction of System Controller IO description
2018-10-24v.11John Hartfiel
  • Note USB3

2018-09-19

v.9John Hartfiel
  • add default SI5338 clk table

2018-06-07

v.8John Hartfiel
  • replace B2B connector section
2017-05-28v.6Jan Kumann
  • Absolute and recommended ratings added.
  • Main components section improved. New top PCB image.
  • Power rails section improved.
  • New physical dimensions images.
2017-02-07

v.1

Jan Kumann
  • Initial document.
--all

Page info
infoTypeModified users
typeFlat

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