Page History

Scroll Ignore

Download PDF version of this document.

Scroll pdf ignore

Table of Contents

Table of Contents

Overview

Scroll Only (inline)
Refer to https://

...

wiki.trenz-electronic.de/

...

display/

...

PD/TE0713+TRM for the online version of this manual and the rest of available documentation.

Trenz Electronic TE0713 is an industrial-grade FPGA module integrating Xilinx Artix-7 FPGA, USB 3.0 to FIFO bridge, 1 GByte of DDR3 DDR3L SDRAM, 32 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Block Diagram

Image Removed

Main Components

Image Removed Image Removed

...

.

...

Key Features

Xilinx Artix-7 (15T to 200T) SoM (System on Module)series FPGA
Both industrial and commercial temperature ranges available
Rugged for high shock and high vibration resistance
1 GByte DDR3 DDR3L 32-bit SDRAM
32 MByte QSPI Flash memory (with XiP support)
USB 3.0 to FIFO interface bridge
Programmable clock quad generator
- GTP transceiver clock (default 125 MHz)
- Fabric clock (default 200 MHz)
Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
152 FPGA I/Os (75 differential pairs) available via B2B connectors
4 GTP (multi Gigabit transceiver) lanes
External clock input for GTP transceivers via B2B connector
On-board high-efficiency DC-DC converters
System management and power sequencing
eFUSE bit-stream encryption
AES bit-stream encryption
User configurable LED
Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Image Added

Page break

Main Components

Image Added Image Added

Xilinx Artix-7 XC7A series FPGA, U1
32 MByte QSPI Flash memory, U4
30.000 MHz quartz crystal, Y1
System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3
Green LED (SYSLED1), D1
4 Gbit DDR3L 256M x 16 SDRAM, U15
Altera Enpirion 12A PowerSoC DC-DC converter, U14
Silicon Labs programmable quad clock generator, U2
SiTime low-power programmable oscillator @ 25.000000 MHz, U9
4 Gbit DDR3L 256M x 16 SDRAM, U19
Samtec Razor Beam™ LSHM-150 B2B connector, JM1
Samtec Razor Beam™ LSHM-150 B2B connector, JM2
Samtec Razor Beam™ LSHM-130 B2B connector, JM3
FTDI USB 3.0 to FIFO interface bridge, U11
Texas Instruments 3A step-down converter (DDR_PWR), U7
Texas Instruments 3A step-down converter (1.8V), U5
Texas Instruments 3A step-down converter (1.2V_MGT), U8
Texas Instruments 3A step-down converter (1V_MGT), U6
Texas Instruments PFET load switch, Q1

Initial Delivery State

Programmable unit	Content	Notes
Xilinx Artix-7 FPGA	Not programmed	U1
System Controller CPLD	Programmed	U3
SPI Flash OTP area	Empty	U4
SPI Flash main array	Empty	U4
SPI Flash Quad Enable bit	Set	U4

...

FPGA Bank	B2B Connector	I/O Signal Count	Voltage Level	Notes
13	JM1	14	VCCIO13	Supplied by the baseboard.
13	JM2	18	VCCIO13	Supplied by the baseboard.
13	JM3	2	VCCIO13	Supplied by the baseboard.
14	JM1	8	3.3V
14	JM3	12	3.3V
15	JM2	48	VCCIO15	Supplied by the baseboard.
15	JM2	2	VCCIO15	Supplied by the baseboard.
16	JM1	48	VCCIO16	Supplied by the baseboard.

...

JTAGEN pin in B2B connector JM1 is used to select JTAG access for FPGA or SC System Controller CPLD:

JTAGEN	JTAG Access To
Low	Artix-7 FPGA
High	System Controller CPLD

Page break

System Controller I/O Pins

...

Pin Name	Mode	Function	Default Configuration
PGOOD	Output	Power good	Active high when all on-module power supplies are working properlyPower Good Pin is zero, if RESIN, EN1, PG_SENSE or PG_DDR_PWR are low, else high impedance. EN1 is also used to enable 1V Power (connected directly outside of the CPLD).
JTAGEN	Input	JTAG select	Low for normal operation, high for System Controller CPLD access.
EN1	Input	Power Enable	When forced low, pulls PROG_B low to emulate power on reset.
RESIN			When forced low, pulls PROG POR_B low to emulate power on reset.
NOSEQ	-	No function	Not used.
MODE	-	No function	Not used.

Note: Pin functionality depends on the running CPLD Firmware, newest one is described here TE0713 CPLD

On-board LEDs

The TE0713-01 module has one LED which is connected to the System Controller CPLD. Once FPGA configuration has completed, it can be used by the user's design.

...

On-board Si5338 clock generator chip is used to generate clocks with 25 MHz oscillator connected to the pin IN3 as input reference. There is a I2C I²C bus connection between the FPGA bank 14 (master) and clock generator chip (slave) which can be used to program output frequencies. See the reference design for more information.

CLK Output	FPGA Bank	FPGA Pin	IO Standard	Net Name	Default Freq	Note
CLK0	-	-	-	-	--	N.C.
CLK1	-	-	-	-	--	N.C.
CLK2	216	F6/E6	Auto	MGT_CLK0_P/N	125 MHz	GTP transceiver clock.
CLK3	35	H4/G4	LVDS	PLL_CLK_P/N	200 MHz	AC coupled, board termination

On-board Peripherals

32 MByte Quad SPI Flash Memory

...

System Controller CPLD (Lattice Semiconductor MachXO2-256HC, U3) is used to control FPGA configuration process. The FPGA is held in reset (by driving the PROG_B signal low) until all power supplies have stabilized.

By driving signal RESIN to low you can reset the FPGA. This signal can be driven from the user’s baseboard PCB via the B2B connector JM2 pin 18.

Input EN1 is also gated to FPGA reset, should be open or pulled up for normal operation. By driving EN1 low, on-board DC-DC converters will be not turned off.

User can create their own System Controller design using Lattice Diamond software. Once created it can be programmed into CPLD via JTAG interface.

CPLD Firmware description:

TE0713 CPLD Firmware
- TE0713 CPLD

DDR3L

...

SDRAM

The TE0713-01 SoM has two 4 Gbit volatile DDR3 SDRAM ICs (U15 and U19) for storing user application code and data.

...

TE0713-01 is equipped with the FTDI FT600Q high performance USB 3.0-to-FIFO interface bridge chip.

FTDI doesn't support 245 Synchronous FIFO mode on TE0713, please use FT60X Chip Configuration Programmer to change Mode into “Multi-Channel FIFO mode”.

Info
SSTX_P and SSTX_N ar swapped on the PCB,this will be corrected automatically on link training on USB3

Power and Power-On Sequence

...

See Xilinx datasheet DS181 - "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0713 module.

Page break

Power Rails

Power Rail Name	B2B Connector JM1 Pin	B2B Connector JM2 Pin	Direction	Notes
VIN	1, 3, 5	2, 4, 6, 8	Input	SoM supply voltage (from the baseboard).
3.3VIN	13, 15	-	Input	SoM supply voltage (from the baseboard).
DDR_PWR	-	19	Output	Module internal supply of 1.35V level.
1V	-	-	-	Module internal supply of 1V level.
1V_MGT	-	-	-	Module internal supply of 1V for bank 216 transceivers.
1.2V_MGT	-	-	-	Module internal supply of 1.2V for bank 216 transceivers.
1.8V	39	-	Output	Module internal 1.8V level. Maximum 300mA available.
3.3V	-	10, 12	Output	Module internal 3.3V level.
VCCIO13	-	1, 3	Input	High-Range bank supply voltage (from the baseboard).
VCCIO15	-	7, 9	Input	High-Range bank supply voltage (from the baseboard).
VCCIO16	9, 11	-	Input	High-Range bank supply voltage (from the baseboard).
VREF_JTAG	-	91	Output	JTAG reference voltage (3.3V).

Board to Board Connectors

Include Page

IN:Samtec LSHM

	4 x 5 SoM LSHM B2B Connectors
	4 x 5 SoM LSHM B2B Connectors

Variants Currently In Production

Module Variant	FPGA	Junction Temperature	Temperature Range
TE0713-01-100-2C	XC7A100T-2FGG484C	0°C to 85°C	Commercial grade
TE0713-01-200-2C	XC7A200T-2FBG484C	0°C to 85°C	Commercial grade

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Units	Reference Document
VIN supply voltage

-0.3

7.0

V

See EN63A0QI and TPS82085 datasheets.

3.3VIN supply voltage

V Storage temperature (ambient)

	-0.5	3.75	V	See LCMXO2-256HC datasheet.
HR I/O banks supply voltage (VCCO)	-0.5	3.6	V	Xilinx datasheet DS181
HR I/O banks input voltage	-0.4	VCCO + 0.55	V	Xilinx datasheet DS181
GTP transceivers Tx/Rx input voltage	-0.5	1.26	V	Xilinx datasheet DS181
Storage temperature	-55	100	°C

See IM4G16D3FABG

See IM4G16D3FABG datasheet.

Recommended Operating Conditions

Parameter	Min	Max	Units	Reference Document
VIN supply voltage

2.5

6.0

V

See TPS82085 datasheet.

3.3VIN supply

voltage V

voltage	2.375	3.6	V	See LCMXO2-256HC datasheet.
HR I/O banks supply voltage (VCCO)	1.14	3.465	V	Xilinx datasheet DS181
HR I/O banks input voltage	-0.20	VCCO + 0.2	V	Xilinx datasheet DS181

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Note
Assembly variants for higher storage temperature range are available on request.

Page break

Physical Dimensions

Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters.

Image Removed Image Removed

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Image Added Image Added

Weight

21 g Plain module.

8.8 g Set of nuts and bolts.

...

Date	Revision	Notes	PCN	Documentation Link
2016-06-30	01	First production revision			TE0713-01

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History

Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
prefix	v.
type	Flat

Page info

infoType	Modified by
type	Flat

Note USB3

2019-07-03

v.13

John Hartfiel

History bugfix
Correction of System Controller IO description

2018-10-24

v.11

John Hartfiel

Note USB3

2018-09-19

v.9

John Hartfiel

add default SI5338 clk table

2018-06-07

v.8

John Hartfiel

replace B2B connector section

2017-05-28

v.6

Jan Kumann

Absolute and recommended ratings added.
Main components section improved. New top PCB image.
Power rails section improved.
New physical dimensions images.

2017-02-07

v.1

Jan Kumann

Initial document.

--

all

Page info

infoType	Modified users
type	Flat

--

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

Trenz Electronic Documentation

Versions Compared

Old Version 3

New Version Current

Key

Overview

Block Diagram

Main Components

Key Features

Block Diagram

Main Components

Initial Delivery State

System Controller I/O Pins

On-board LEDs

On-board Peripherals

32 MByte Quad SPI Flash Memory

DDR3L

SDRAM

Power and Power-On Sequence

Power Rails

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Physical Dimensions

Operating Temperature Ranges

Weight

Document Change History

Disclaimer