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The Trenz Electronic TEBA0841 Carrier Board is a base-board for 4x5 4 x5 SoMs, which is dedicated to test- and evaluation-purposes of Multi-gigabit transceiver units of Trenz Electronic 4x5 SoMs.
This base-board provides also soldering-pads as place-holders for pin-headers as option to get access to the MIO-, PS- und and PL-IO-banks of the mounted SoM.
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- Samtec Razor Beam™ LSHM-150 B2B connector JB1
- Samtec Razor Beam™ LSHM-150 B2B connector JB3
- Samtec Razor Beam™ LSHM-130 B2B connector JB2
- 6-pin header J26 for selecting VCCIOA supply-voltage
- 6-pin header J27 for selecting VCCIOD supply-voltage
- Micro USB Connector J12 (Device or OTG mode)
- JTAG header, connected to JTAG interface of 4x5 4 x 5 Module (XMOD FTDI JTAG Adapter compatible pin assigment-assignment)
- User LED D1 (green)
- User LED D2 (red)
- SFP+ Connector J1
- 50-pin header soldering-pads J17 for access to SoM's IO-banks (LVDS-pairs possible)
- 50-pin header soldering-pads J20 for access to SoM's IO-banks (LVDS-pairs possible)
- 16-pin header soldering-pads J3, XMOD FTDI JTAG Adapter compatible pin assigment -assignment with 2 additional pins for reference-clock input to 4x5 SoM
- 10-pin header soldering-pads J4 for access to SoM's SDIO-port (voltage translation via SDIO Port Expander necessary)
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- SFP+ connector (Enhanced small form-factor pluggable), supports data transmission rates up to 10 Gbit/s
- Micro-USB-Interface (J10) connected to Zynq-module (Device or OTG mode)
- Trenz 4x5 module Socket (3 x Samtec LSHM series connectors)
- 4x5 SoM programable by JTAG header (JX1)
- 2 x user LEDs routed to MIO-pins of the SoM
- Soldering-pads J17 and J20 as place-holder for further possibilities to access to SoMs IO-bank-pins, usable as LVDS-pairs
- Soldering-pads J3 and J4 as place-holder for access to JTAG- or SDIO-port of the SoM
Interfaces and Pins
Micro SD Card Socket
Micro SD Card socket is not directly wired to the B2B connector pins, but through a Texas Instruments TXS02612 SDIO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq-module. The Micro SD Card has 3.3V signal voltage level, but the MIO-bank on the Xilinx Zynq-module has VCCIO 1.8V.
Dual channel USB to UART/FIFO
The TE0705 Carrier Board has on-board USB 2.0 High Speed to UART/FIFO IC FT2232HQ from FTDI. Channel A can be used as JTAG-Interface (MPSSE) to program the System-Controller-CPLD, Channel B can be used as UART-Interface routed to CPLD. There are also 6 additionally bus-lanes available for user-specific use. The FT2232HQ-Chip can also be used as FIFO in FT245 asynchronous mode.
There is also a standard 256 Byte EEPROM connected to the FT2232HQ-chip available to store custom configuration settings. EEPROM settings can be changed using FTDI provided tools that can be downloaded from FTDI website. See FTDI website for more information.
USB Interface
The TE0705 carrier board has two physical USB-connectors:
- J7 as mini-USB-connector wired to on-board FTDI FT2232HQ chip.
- J12 as micro-USB-connector wired to B2B connector JB3 (there is usually an USB-transceiver on the SoMs).
JTAG Interface
JTAG access to the CPLD and Xilinx Zynq-module is provided via Mini-USB JTAG Interface J7 (FTDI FT2232H) and controlled by DIP switch S3-3.
The JTAG port of the CPLD is enabled by setting switch S3-3 labeled as "ENJTAG" to the OFF-position.
LEDs
There are eight LEDs (D6, D7, D8, D9, D4, D5, D14, D15) available to the user. All LEDs are red colored and connected to the on-board System-Controller-CPLD. Their functions are programmable and depend on the firmware of the System-Controller-CPLD. For detailed information, please refer to the documentation of the TE0705 System-Controller-CPLD.
One green LED D22 shows the availability of the 3.3V supply voltage of the TE0701 Carrier Board.
4-bit DIP-switch S3
On the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (15) in Figure 1) available. The default switch mapping is as follows:
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4-bit DIP-switch S4
Additionally, on the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (16) in Figure 1) available. The signals of the switch are routed to carrier board's System-Controller-CPLD and are fully user-configurable depending on a customer developed CPLD-firmware. Please refer to the documentation of the TE0705 System-Controller-CPLD to get information how to put these user-switches in operation.
User-Push-Buttons
On the TE0705 Carrier Board there are two push buttons (S1 and S2) and are routed to the System-Controller-CPLD and available to the user. The default mapping of the push buttons is as follows:
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If S2 is pushed, the active-high Power ON (PON) signal (that is internally pulled-up) will be deasserted, which can be considered as a "RESTART" button to switch off (push button) and on (release button) all on-module power supplies (except 3.3VIN). Note: The capability of the switch to be enabled the first time will become active shortly after Power on Reset (POR).
| Info |
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The active-high PON signal is directly mapped to the active-high EN1 signal which is routed to the module's SC-CPLD (e.g., on the TE0720) and directly used (after deglitching) as a mandatory active-high enable signal to the power FET switch (3.3VIN -> 3.3V) as well as the DC-DC converters (VIN -> 1.0V, 1.5V, 1.8V). |
By closing jumper J4 the PON-signal will be permanently deasserted, hence the power FET switch and the DC-DC converters on module will be disabled.
The functionality of the push buttons depends on the CPLD-firmware. For detailed information of the function of the push buttons, please refer to the documentation of the TE0705 System-Controller-CPLD.
Ethernet
The TE0701 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J14) with two LEDs.
On-board Ethernet MagJack J14 pins are routed to B2B connector JB1 via MDI. The center tap of the Magnetics is not connected to module's B2B connector.
PHY LEDs are not connected directly to the module's B2B connectors as the 4x5 module have no dedicated PHY LED pins assigned. PHY LEDs are connected to the TE0705 System-Controller-CPLD, that can route those LEDs to some module's I/O Pins. In that case the CPLD has to map the PHY LEDs to corresponding pins.
See documentation of the TE0705 System-Controller-CPLD to get information of the function of the PHY LEDs.
IDC header sockets J5 and J6
J5 and J6 sockets signal routing is done as differential pairs for pins 1-3, 2-4, 5-7, 6-8. The differential pairs are operable with VCCIO-voltage VIOTB.
Please use Master Pinout Table table as primary reference for the pin mapping information.
IDC header socket J1
Zynq-module's MIO0-bank pins MIO0, MIO9-MIO15 are accessible on socket J1. Maximal VCCIO-voltage is 3.3V on this socket. An exception here is the MIO12-pin, which is buffered with a Schmitt-Trigger-Buffer with a Hystersis of 5.0V.
IDC header socket J2
Zynq-module's PL IO-bank pins are accessible on socket J2. The IO-signals are routed from this socket to B2B-connector JB3 and are only single-ended IOs, hence this signal-pins are not usable as differential pairs. Maximal VCCIO-voltage is VIOTB on this socket.
40-pin headers J11 and J13
40-Pin-Header J11 and J13 for access to Zynq-module's PL IO-bank-pins on B2B-connectors JB1 and JB2. Operable with fixed (3.3V) or adjustable VCCIO-voltage VIOTB (not usable as LVDS-pairs, only single-ended IOs).
Power
Power Supply
Power supply with minimum current capability of 3A at 12V for system startup is recommended.
Power-On Sequence
The on-board voltages of the carrier board will be powered up simultaneously after one single power-supply with a nominal voltage of 12V is connected to the power-jack J10.
The PL IO-bank supply voltage FMC_VADJ will be available after the output of the 5.0V-DCDC-converter is active and the pin EN_FMC of the SC-CPLD is asserted.
Figure 3: Power-Up sequence diagram
Configuring VCCIO
On the TE0705 carrier board different VCCIO configurations can be chosen by jumper J21 and DIP-switch S3.
The purpose of the jumper and the DIP-switch S3 of the Carrier Board will be explained in the following sections.
Select VCCIO-voltage by DIP-Switch S3
There is the possibility to select the module's PL IO-bank's supply voltage VIOTB to fixed adjustable voltages VADJ. Therefore, the jumper J21 has to be set to the position 1, 2-3, to connect the pins 'VIOTB' and 'ADJ'. On position 1-2, 3, the supply voltage VIOTB will be fixed to 3.3V
Table 3 shows the switch-configuration of the DIP-switch S3 to set the voltage VADJ.
Note: The configuration of VADJ depends on the used firmware of the System-Controller-CPLD. For detailed information, refer to the documentation of the TE0705 System-Controller-CPLD.
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S3-1 (CM1)
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S3-2 (CM2)
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VADJ Value
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OFF
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OFF
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1.8V
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OFF
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ON
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2.5V
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ON
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OFF
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3.3V
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ON
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ON
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1.8V (Note: Also Zynq-module's SC-CPLD JTAG-access is enabled, see section JTAG in the documentation of the TE0705 System-Controller-CPLD.)
Table 3: Switch S3 positions for fixed values of the VADJ voltage
Configuring Power Supply of the Micro USB Connector (Device, Host or OTG Modes)
The TE0705 carrier board can be configured as a USB host. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro USB port on J12). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the overcurrent logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 100µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K (J9: 1-2, 3) or 10K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY on the mounted SoM, which is, in turn, connected to the Zynq FPGA. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (100 µF added).
Additionally, the TE0705 carrier board is equipped with a second mini USB port J7 that is connected to a "USB to multi-purpose UART/FIFO IC" from FTDI (FT2232HQ) and provides a USB-to-JTAG interface between a host PC and the TE0705 carrier board and the Zynq-module, respectively. Because it acts as a USB function device, no power switch is required (and only a ESD protection must be provided) in this case.
Summary of VCCIO-configuration
On the TE0705 carrier board all PL IO-bank's supply voltages of the 4x5 SoM (VCCIOA, VCCIOB, VCCIOC, VCCIOD; see 4x5 Module Integration Guide) are connected to the VCCIO-voltage VIOTB, which is either fixed to 3.3V (J21: 1-2, 3) or selectable with the adjustable supply-voltage VADJ (J21: 1, 2-3). The supply-voltages have following pin assignments on B2B-connectors:
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base-board
supply-voltages
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base-board voltages and signals connected with
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JB1-10, JB1-12,
JB2-2, JB2-4, JB2-6,
JB2-8, JB2-10
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VCCIOA (JM1-9, JM1-11),
VCCIOB (JM2-1, JM2-3), VCCIOC (JM2-5),
VCCIOD (JM2-7, JM2-9)
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VCCIO3 (Systm-Controller-CPLD pin 5, 11, 23),
J15 VTREF,
J11, J13, J2, J5 and J6 VCCIO
Table 4: base-board supply-voltage VIOTB
| Note |
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Note: The corresponding PL IO-voltage supply voltages of the 4x5 SoM to the selectable base-board voltage VIOTB are depending on the mounted 4x5 SoM and varying in order of the used model. Refer to SoM's schematic to get information about the specific pin assignment on module's B2B-connectors regarding PL IO-bank supply voltages and to the 4x5 Module integration Guide for VCCIO voltage options. |
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base-board supply-voltages vs voltage-levels
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(J20: 1-2: additional decoupling-capacitor 100 µF)
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Table 5: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2, 3' means pins 1 and 2 are connected, 3 is open. 'Jx: 1, 2-3' means pins 2 and 3 are connected, 1 is open
| Note |
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| It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4x5 module to avoid failures and damages to the functionality of the mounted SoM. |
Power On Reset (POR)
On the TE0705 the 5.0V and 3.3V power supply rails are generated by high performance DC-DC-converters from the external 12V supply. While the 3.3V plane supplies several on-board components (e.g., Lattice CPLD and FTDI Dual USB UART/FIFO IC), the 5V plane is mainly provided to power supply of the module to be carried (e.g., TE0720 Zynq SoC module). For the latter, however, special considerations must be taken (see TE0720 Power Supply). Therefore, the on-module system controller (SC) must be provided with information about the power-on-reset (POR) process, namely, the following control signals EN1, RESIN, and NOSEQ. And the SC provides, in turn, the status signal PGOOD down to the on-board System-Controller-CPLD.
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This signal is controlled by the user push button S1 on the TE0701 and is forwarded directly to the SC, where it is latched together with the EN1 signal as well as the “all power rails OK” signal (1.0V and 1.8V for core; 1.5V and VTT for RAM, and 3.3V).
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The 3.3V power supply rail can be switched on (EN_3V3=’1’) or off (EN_3V3=’0’) by a load switch (TPS27082L) and is continuously checked by a voltage detector (TPS3805H33). Note: The 3.3VIN power supply (from which the 3.3V power plane is sourced) is supplied by the TE0701 Carrier Board and is kept always on! |
When RESIN (alias user push button S1) is not pushed and simultaneously the EN1 signal is asserted (EN='1') and all power rails are ok, the active-high Zynq power-on-reset signal PS_POR_B is asserted.
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SFP+ Connector
On the TEBA0841 Carrier Board is a SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded into a SFP cage J2 (board-rev. 01: Molex 74737-0009).
The RX-/TX-data-lanes are connected to B2B-connector JB2, the control-lines are connected to pins on B2B-connector JB1 and are MIO-pins in standard TE module's pin-assignment.
On this SFP+ connector, on both 4 x 5 SoMs TE0741 and TE0841 MGT-lane 3 is accessible.
The pin-assignment of the SFP connector is in detail as fellows:
| SFP+ pin | SFP+ pin netname | B2B |
|---|---|---|
| Transmit Data + (pin 18) | MGT_TX3_P | JB2-26 |
| Transmit Data - (pin 19) | MGT_TX3_N | JB2-28 |
| Receive Data + (pin 13) | MGT_RX3_P | JB2-25 |
| Receive Data - (pin 12) | MGT_RX3_N | JB2-27 |
| Receive Fault (pin 2) | MIO10 | JB1-96 |
| Receive disable (pin 3) | not connected | - |
| MOD-DEF2 (pin 4) | MIO13 | JB1-98 |
| MOD-DEF1 (pin 5) | MIO12 | JB1-100 |
| MOD-DEF0 (pin 6) | MIO11 | JB1-94 |
| RS0 (pin 7) | not connected | - |
| LOS (pin 8) | MIO0 | JB1-88 |
| RS1 (pin 9) | not connected | - |
Table 1: SFP+ connector pin-assignment
Bridged MGT-Lanes on B2B Connector JB2
The TEBA0841 Carrier Board is mainly for the 4 x 5 SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on their FPGA-modules with up to 8 available MGT-lanes. To test this MGT-lanes, the RX/TX differential pairs are bridged, hence the transmitted data on this MGT-lanes are received simultaneously by the same MGT-lane.
The MGT-lane pins are bridged as fellows, if 4 x 5 SoM TE0741 is mounted:
| MGT-lane | B2B TX diff-pair | B2B RX diff-pair | B2B-pins bridged |
|---|---|---|---|
| MGT-lane 0 | JB2-8 (MGT_TX0_N) JB2-10 (MGT_TX0_P) | JB2-7 (MGT_RX0_N) JB2-9 (MGT_RX0_P) | JB2-7 to JB2-8 bridged JB2-9 to JB2-10 bridged |
| MGT-lane 1 | JB2-14 (MGT_TX1_N) JB2-16 (MGT_TX1_P) | JB2-13 (MGT_RX1_N) JB2-15 (MGT_RX1_P) | JB2-13 to JB2-14 bridged JB2-15 to JB2-16 bridged |
| MGT-lane 2 | JB1-20 (MGT_TX2_N) JB1-22 (MGT_TX2_P) | JB1-19 (MGT_RX2_N) JB1-21 (MGT_RX2_P) | JB1-19 to JB1-20 bridged JB1-21 to JB1-22 bridged |
| MGT-lane 7 | JB1-3 (MGT_TX7_P) JB1-5 (MGT_TX7_N) | JB1-9 (MGT_RX7_P) JB1-11 (MGT_RX7_N) | JB1-3 to JB1-9 bridged JB1-5 to JB1-11 bridged |
| MGT-lane 6 | JB1-15 (MGT_TX6_P) JB1-17 (MGT_TX6_N) | JB1-21 (MGT_RX6_P) JB1-23 (MGT_RX6_N) | JB1-15 to JB1-21 bridged JB1-17 to JB1-23 bridged |
Table 2: Bridging-table of the MGT-lanes for mounted 4 x 5 SoM TE0741.
| Note |
|---|
| Note: The MGT-lanes of 4 x 5 SoM TE0841 have other designations. |
USB Interface
The TEBA0841 carrier board has one physical USB-connector J10, which is available as Micro-USB port. The USB interface J10 can be operated in Device- and OTG-modes. The Micro-USB port-pins are routed to the USB-OTG-interface on B2B-connector JB2. There are usually corresponding USB-PHYs on SoMs supported by the Carrier Board TEBA0841.
JTAG Interface
The JTAG-interface of the mounted 4 x 5 SoM can be accessed via header JX1. This header has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment.
| JX1 pin | JX1 pin net name | B2B |
|---|---|---|
| C (pin 4) | TCK | JB3-100 |
| D (pin 8) | TDO | JB3-98 |
| F (pin 10) | TDI | JB3-96 |
| H (pin 12) | TMS | JB3-94 |
| A (pin 3) | MIO15 | JB1-86 |
| B (pin 7) | MIO14 | JB1-91 |
| E (pin 9) | BOOTMODE | JB1-90 |
| G (pin 11) | RESIN | JB3-17 |
Table 3: JTAG header JX1 pin-assignment
There is also the option to mount and solder a 2-row 16-pin header to the place-holder J3, which has the same pin-assignment as header JX1, but with also two additional pins (15,16) as LVDS-pair, to put an external reference clock-signal to the mounted 4 x 5 SoM. The clock-signal is put to to the SoM via B2B-connector pins JB2-32 (MGT_CLK0_N) and JB2-34 (MGT_CLK0_P).
On both interfaces (JX1, J3), the pins with the net-names MIO14 and MIO15 are available as user IO's which could be used as UART-interface for example.
LEDs
There are two LEDs D1 (green) and D2 (red) available to the user. The green LED D1 is connected to the pin MIO9 (JB1-92), the red LED D2 is connected to the pin JB3-90 with the net name 'RLED'.
Header place-holder J4
The place-holder J4 with solder-pads to mount a 2-row 10-pin header provides the capability, to access via this header the SDIO-port of the mounted 4 x 5 SoM, if available. For this purpose, there is also voltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary due to the different voltage levels of the Micro SD Card (3.3V) and MIO bank of the Xilinx Zynq-chip (1.8V).
Header place-holder J17 and J20
The place-holders J17 and J20 with solder-pads to mount 2-row 50-pin headers provide the capability to access the PL IO-bank pins of the mounted 4 x 5 SoM.
With mounted header J17 there are 42 IO's of PL-IO-bank 13 of the 4 x 5 SoM available (B2B-connector JB3), which are also usable as 21 LVDS-pairs. On this header the IO's are operable with fixed (3.3V) or selectable VCCIO-voltage VCCIOD.
On header J20 there are 42 IO's available of PL-IO-bank 35 (B2B-connector JB1). This IO's are also usable as 21 LVDS-pairs and operable with fixed (3.3V) or selectable VCCIO-voltage VCCIOA.
Power
Power Supply
Power supply with minimum current capability of 3A at 12V for system startup is recommended.
Power-On Sequence
The on-board voltages of the carrier board will be powered up simultaneously after one single power-supply with a nominal voltage of 12V is connected to the power-jack J10.
The PL IO-bank supply voltage FMC_VADJ will be available after the output of the 5.0V-DCDC-converter is active and the pin EN_FMC of the SC-CPLD is asserted.
Figure 3: Power-Up sequence diagram
Configuring VCCIO
On the TE0705 carrier board different VCCIO configurations can be chosen by jumper J21 and DIP-switch S3.
The purpose of the jumper and the DIP-switch S3 of the Carrier Board will be explained in the following sections.
Summary of VCCIO-configuration
On the TE0705 carrier board all PL IO-bank's supply voltages of the 4x5 SoM (VCCIOA, VCCIOB, VCCIOC, VCCIOD; see 4x5 Module Integration Guide) are connected to the VCCIO-voltage VIOTB, which is either fixed to 3.3V (J21: 1-2, 3) or selectable with the adjustable supply-voltage VADJ (J21: 1, 2-3). The supply-voltages have following pin-assignments on B2B-connectors:
base-board supply-voltages | base-board B2B connector-pins | standard assignment of PL IO-bank supply-voltages on TE 4x5 module's B2B connectors | base-board voltages and signals connected with |
|---|---|---|---|
| VIOTB | JB1-10, JB1-12, JB2-2, JB2-4, JB2-6, JB2-8, JB2-10 | VCCIOA (JM1-9, JM1-11), VCCIOB (JM2-1, JM2-3), VCCIOC (JM2-5), VCCIOD (JM2-7, JM2-9) | VCCIO3 (Systm-Controller-CPLD pin 5, 11, 23), J15 VTREF, J11, J13, J2, J5 and J6 VCCIO |
Table 4: base-board supply-voltage VIOTB
| Note |
|---|
Note: The corresponding PL IO-voltage supply voltages of the 4x5 SoM to the selectable base-board voltage VIOTB are depending on the mounted 4x5 SoM and varying in order of the used model. Refer to SoM's schematic to get information about the specific pin-assignment on module's B2B-connectors regarding PL IO-bank supply voltages and to the 4x5 Module integration Guide for VCCIO voltage options. |
Following table describes how to configure the base-board supply-voltages by jumpers:
base-board supply-voltages vs voltage-levels | VIOTB | USB-VBUS |
|---|---|---|
| 3V3 | J21:1-2, 3 | - |
| VADJ | J21:1, 2-3 | - |
| 5V0 intern | - | J9:1-2, 3 & J19: 1-2 (J20: 1-2: additional decoupling-capacitor 100 µF) |
| Vbus extern | - | J9: 1, 2-3 & J19: open |
Table 5: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2, 3' means pins 1 and 2 are connected, 3 is open. 'Jx: 1, 2-3' means pins 2 and 3 are connected, 1 is open
| Note |
|---|
| It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4x5 module to avoid failures and damages to the functionality of the mounted SoM. |
Table 6: Generation of PGOOD-signal
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Technical Specifications
Absolute Maximum Ratings
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| date | revision | authors | description |
|---|---|---|---|
| 2017-0102-1810 | Ali Naseri | current TRM for TE0705TEBA0841-0401 | |
| 2017-01-1530 | 0.1 | Ali Naseri | Initial document |
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