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Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Storage device name

Content

Notes

QSPI Flash

Empty

 

Signals, Interfaces and Pins

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On-board I2C interface is provided via ZYNQ SoC PS bank 501 pins MIO36 (SCL) and MIO37 (SDA). I2C addresses for on-board devices are listed in the table below:

I2C DeviceI2C AddressNotes
 Si1143-A11-GMR0x5A 

JTAG Interface

JTAG access to the Xilinx ZYNQ XC7Z010 SoC is provided through J2 connector.

JTAG Signal

J2 Connector Pin

TCK 4
TDI 9
TDO 10
TMS 8

LEDs

LEDColorConnected ToDescription and Notes
D1RedLED2, U4 
D2

Green

MIO7, U1User controlled, default OFF (when PS7 has not been booted).
D3

Red

LED1, U4

 
D4RGB

RGB_R, U1

RGB_G, U1

RGB_B, U1

 
D5RedLED3, U4 

D6

Green

DONE, U1

Reflects inverted DONE signal. ON when FPGA is not configured,

OFF as soon as PL is configured.

Default MIO Mapping

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

  
-0.53.6

V

See Xilinx datasheet DS187, "Zynq-7000 All Programmable SoC: DC and AC Switching Characteristics".

Storage temperature

-40

+85

°C

-
Same as above.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply
Supply voltage
   V
1.143.465 VSee Xilinx datasheet DS187, "Zynq-7000 All Programmable SoC: DC and AC Switching Characteristics".
Operating temperature0+85°CCommercial range devices.
Operating temperature-40+100°CIndustrial range devices.
 
Note
Assembly variants for higher storage temperature range are available on request.

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Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
2015-10-2302   
 

01

 

  

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.


Document Change History

Date

Revision

Contributors

Description

2017-02-09

Jan Kumann

Initial document.

Disclaimer

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IN:Legal Notices
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