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Table of Contents

Overview

Refer to https://wiki.trenz-electronic.de/display/PD/TE0722+TRM for downloadable version of this manual and additional technical documentation of the product.

The Trenz Electronic TE0722-02 is a DIPFORTy1 "Soft Propeller" based on the Xilinx Zynq-7000 SoC.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE022-02 block diagram.

Main Components

Figure 2: TE0722-02 PCB top side.

Figure 3: TE0722-02 PCB bottom side.

  1. Xilinx Zynq XC7Z010 or Zynq XC7Z007S SoC, U1
  2. Micro SD card socket with card detect, J8
  3. Red LED, D3
  4. Green LED, D2
  5. Red LED, D6
  6. 20-pin connector placeholder, P1
  7. Red LED, D5
  8. Proximity/ambient light sensor, U4
  9. RGB LED, D4
  10. Red LED, D1
  11. 20-pin connector placeholder, P2
  12. Ultra-low supply-current voltage monitor, U4
  13. 2 x 5-pin connector placeholder, J1
  14. 2 x 5-pin connector placeholder, J2
  15. 2 x 5-pin connector placeholder, J3
  16. 16 MByte QSPI Flash memory, U5
  17. Low-power programmable oscillator @ 33.333333 MHz, U8
  18. 1A PowerSoC DC-DC converter (1.0V), U2
  19. 1A PowerSoC DC-DC converter (1.8V), U3

Initial Delivery State

Storage device name

Content

Notes

Quad SPI Flash

Empty

 

Table 1: Initial delivery state of programmable devices on the module

Boot Process

The 7 boot mode strapping pins (MIO2 ... MIO8) of the Xiliny Zynq Z-7010 device are hardware programmed on the board. They are evaluated by the Zynq device soon after the 'POR_B'.signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).

The TE0722 FPGA board is hardware programmed to boot initially from the on-board QSPI Flash memory U5. The JTAG interface of the module is provided for storing the data to the QSPI Flash memory through the Zynq device.

Signals, Interfaces and Pins

I/O Signals on Connectors

Overview of the PL I/O banks signals routed to the external connectors:

BankTypeConnectorI/O Signal CountVoltageNotes
34HRP183.3VSignal Schematic names: 'P0' - 'P7'
34HRP283.3VSignal Schematic names: 'P24' - 'P31'
34HRP210 single ended I/O's or 5 differential pairs3.3V -
34HRJ163.3VSignal Schematic names: 'X2A' - 'X2F'
34HRJ223.3V -
34HRJ343.3VSignal Schematic names: 'X1A' - 'X1D'
35HRP18 single ended I/O's or 4 differential pairs3.3V -

Table 2: Zynq SoC PL I/O signals overview

Zynq SoC I/O Banks

BankTypeVCCIOI/O Signal CountAvailable on ConnectorsNotes
34HR3.3V413838 user I/O's, 3 I/O's used for controlling the RGB LED D4. 
35HR3.3V888 single ended or 4 differential.
500PS MIO3.3V7-6 MIO pins used for QSPI flash memory interface, 1 MIO pin connected to green LED D2.
501PS MIO3.3V10-7 MIO pins used for SD Card interface, 3 MIO pins connected to light sensor U4.
0Config3.3V5-4 I/O's are dedicated to JTAG interface, 'DONE'-signal is indicated by red LED D6.

Table 3: General overview of Zynq SoC PL/PS I/O banks

JTAG Interface

JTAG access to the Xilinx ZYNQ XC7Z010 SoC is provided through J2 connector:

JTAG Signal

J2 Connector Pin

TCK 4
TDI 9
TDO 10
TMS 8

Table 4: JTAG interface signals

Quad SPI Interface

Quad SPI Flash memory (U5) is connected to the Zynq SoC PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6:

Zynq SoC's MIO-pinU5 PinSignal Schematic Name
MIO11SPI0-CS
MIO25SPI0-DQ0/M0
MIO32SPI0-DQ1/M1
MIO43SPI0-DQ2/M2
MIO57SPI0-DQ3/M3
MIO66SPI0-SCK

Table 5: Quad SPI interface signals and connections

SD Card Interface

TE0722 board has on-board 3.3V SD Card socket (J8) with card detect switch wired to the Zynq SoC PS MIO bank 501, pins MIO28 .. MIO33 and MIO49.

Zynq SoC's MIO-pinJ8 pinSignal Schematic Name
MIO28J8-7DAT0
MIO29J8-3CMD
MIO30J8-5CLK
MIO31J8-8DAT1
MIO32J8-1DAT2
MIO33J8-2CD/DAT3
MIO49J8-G4Card detect switch

Table 6: SD card interface signals

I²C Interface

I2C interface pins SCL and SDA from the Zynq SoC PS MIO-bank 501 (MIO36, MIO37) are connected to ambient / proximity light sensor (U4).

Zynq SoC's MIO-pinU4 pinSignal Schematic Name
MIO362SCL
MIO371SDA

Table 7: Zynq SoC I2C interface signals

Default PS MIO Mapping

MIO-pinFunctionConnector to
MIO1QSPIQSPI flash memory, pin 1
MIO2QSPIQSPI flash memory, pin 5
MIO3QSPIQSPI flash memory, pin 2
MIO4QSPIQSPI flash memory, pin 7
MIO5QSPIQSPI flash memory, pin 3
MIO6QSPIQSPI flash memory, pin 6
MIO7GPIOGreen LED D2
MIO28SDIOSD Card socket. pin J8-5
MIO29SDIOSD Card socket. pin J8-3
MIO30SDIOSD Card socket. pin J8-7
MIO31SDIOSD Card socket. pin J8-8
MIO32SDIOSD Card socket. pin J8-1
MIO33SDIOSD Card socket. pin J8-2
MIO36I²CAmbient / Proximity Light Sensor U4, pin 2
MIO37I²CAmbient / Proximity Light Sensor U4, pin 1
MIO39GPIOAmbient / Proximity Light Sensor U4, Interrupt pin 4
MIO49GPIOSD Card socket card detect pin J8-G4

Table 8: Default mapping of Zynq PS MIO-bank pins

On-board Peripherals

Quad SPI Flash Memory

On-board QSPI flash memory (U5) is provided by Cypress Semiconductor Serial Flash Memory S25FL127SABMFV101 with 128 MBit (16 MByte) storage capacity. This non volatile memory is used to store initial configuration data. Besides initial configuration data, remaining free flash memory can be used for user application and data storage.

Proximity and Ambient Light Sensor

The TE0722-02 Zynq SoC board is equipped with the Si1143 infrared proximity and ambient light sensor. On-board three red LEDs D1, D3 and D5 are connected to the light sensor to use the proximity sensing functionality. For more details and how to configure and use this chip, refer to the Si1141/42/43 data sheet.

Oscillator

The Zynq SoC board one reference clocking signal as system clock provided by on-board oscillator U8:

Clock SourceFrequencyClock Input Destination
SiTime SiT8008AI Oscillator, U833.333333 MHzZynq PS Bank 500, pin C7

Table 9: Clock sources overview

On-board LEDs

There are 6 LEDs fitted on the Zynq SoC board. The LEDs are user configurable to indicate for example any system status.

LEDColorConnected toSignal Schematic NameDescription and Notes
D1RedLight sensor U4, pin 6- Proximity sensing functionality of light sensor U4
D2

Green

Zynq PS bank 500MIO7user configurable
D3

Red

Light sensor U4, pin 9- Proximity sensing functionality of light sensor U4
D4RGBZynq PL bank 34,
pins J15, L14, K12

RGB_R, U1,

RGB_G, U1,

RGB_B, U1

user configurable
D5RedLight sensor U4, pin 7- Proximity sensing functionality of light sensor U4

D6

Green

Zynq config bank 0

DONE

Reflects inverted DONE signal. ON when FPGA is not configured,
OFF as soon as PL configuration is finished.

Table 10: LEDs of the board

Connectors

All connectors are for 100mil (2.54mm pitch) headers, all connector locations are in 100mil grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

TE0722-02 needs one single power supply with nominal of 3.3V at all variants. Following diagram shows the dependencies of the power supply:


Figure 4: Module power supply dependencies

Power Consumption

Board VariantFPGADesignTypical Power, 25°C ambient
TE0722-02IXC7Z010-1CLG225INot configuredTBD*
TE0722-02XC7Z010-1CLG225CNot configuredTBD*
TE0722-02-07S-1CXC7Z007S-1CLG225CNot configuredTBD*

Table 11: Module power consumption

*TBD - To Be Determined.

The maximum power consumption of the module mainly depends on the design running on the Zynq SoC's FPGA and ambient temperature.

Xilinx provide a power estimator excel sheets to calculate power consumption. It is also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power-On Sequence

There is no specific or special power-on sequence, single power source is needed as 3.3V as power supply voltage.

Voltage Monitor Circuit

The voltages 1.0V (core voltage) and 3.3V are monitored by the voltage monitor circuit U6, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the connector pin P1-10 ('NRST') to GND. Leave this pin unconnected or connect to VDD (3.3V) when unused.

Figure 5Voltage monitor circuit

Power Rails

Power Rail Name

J1 Pins

J2 PinsJ3 PinsP1 PinP2 Pin

Direction

Notes
3.3V5, 65, 65, 61212Input3.3V power supply voltage

Table 12: Board power rails

Bank Voltages

Bank

Bank I/O Voltage VCCO

Voltage Range

0 (config)3.3Vfixed
500 (MIO)3.3Vfixed
501 (MIO)3.3Vfixed
34 (HR)3.3Vfixed
35 (HR)3.3Vfixed

Table 13: Board bank voltages

Variants Currently in Production

 Board VariantXilinx Zynq SoC

ARM Cores

PL Cells

LUTsFlip-FlopsBlock RAM

DSP Slices

Zynq SoC Operating Temp.

Temp. Range

TE0722-02IXC7Z010-1CLG225IA9+ Dual-core28K17,6K35,2K2.1 MBytes80

–40°C to +100°C

Industrial
TE0722-02XC7Z010-1CLG225CA9+ Dual-core28K17,6K35,2K2.1 MBytes80

0°C to +85°C

Commercial
TE0722-02-07S-1CXC7Z007S-1CLG225CA9+ Single-core23K14,4K28,8K1.8 MBytes66

0°C to +85°C

Commercial

Table 14: Board variants

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

3.3 supply voltage

-0.33.6

V

EN5311QI datasheet / Xilinx datasheet DS187
HR PL I/O banks input voltage (VCCIO single ended)-0.4VCCO + 0.55VXilinx datasheet DS187 (VCCO 3.3V nominal)

Storage temperature

-40

+85

°C

Silicon Labs Si1141/42/43 datasheet.

Table 15: Board absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
3.3 supply voltage3.33.465 VXilinx datasheet DS187
HR PL I/O banks input voltage (VCCIO single ended)-0.20VCCO + 0.20VXilinx datasheet DS187 (VCCO 3.3V nominal)

Operating Temperature Commercial
(Variant TE0722-02 and TE0722-02-07S-1C)

0+85°CXilinx datasheet DS190

Operating Temperature Industrial
(Variant TE0722-02I)

-40+85
Xilinx datasheet DS190

Table 16: Board recommended operating condition

Please check Xilinx datasheet DS187 for complete list of absolute maximum and recommended operating ratings for the Zynq-7 device.

Physical Dimensions

 All dimensions are given in millimeters.

 

Figure 6: Board physical dimensions

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-02 - -TE0722-02
 -

01

First production release - -

Table 17: Board hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Figure 7: TE0722 module hardware revision number

Document Change History

Date

Revision

Contributors

Description



Ali Naseri, Jan Kumann

  • First TRM Release

Table 18: Document change history

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