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Overview

Refer to https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TE0705 for downloadable version of this manual and additional technical documentation of the product.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TE0705 Carrier Board.

Block Diagram

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Figure 1: TE0705-04 Block Diagram

Main Components

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Figure 2: 4x5 SoM carrier board TE0705-04

TE0705-04:

carrier board provides functionality for testing, evaluation and development purposes of company's 4 x 5 cm SoMs (System on Module). Carrier board is equipped with broad range of various components and connectors for different configuration setups and needs. On-module functional components and multipurpose I/Os of the SoM PL and PS logic are connected via board-to-board connectors to the carrier board components and connectors for easy user access.

See "4 x 5 cm carriers" page for more information about supported 4 x 5 cm SoMs.

Block Diagram

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Figure 1: TE0705-04 Block Diagram.

Main Components

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Figure 2: 4 x 5 SoM carrier board TE0705-04.

1. ARM JTAG Connector (DS-ARM JTAG Connector (DS-5 D-Stream) J15 - PJTAG to EMIO multiplexing needed
2. 12-pin IDC header socket J1 (right angle, max. VCCIO - voltage : 3.3V): mapped to 8 Zynq PS MIO0-bank-pins (MIO0, MIO9 to MIO15), 6 pins (MIO10 to MIO15) are additionally connected to TE0705 System - Controller - CPLD

3. RJ45 GbE Connector

4. SD Card Socket - Zynq SDIO0 Bootable SD port
5. 12-pin IDC header socket (right angle) J2 for access to Zynq-module's PL IO-bank pins (not usable as LVDS - pairs, only single-ended IOs, max. VCCIO - voltage: VIOTB)
6. Micro USB Connector J12 (Device, Host or OTG Modes)
7. Battery holder for CR1220 (RTC backup voltage)
8. 12-pin IDC header socket (vertical) J5 for access to Zynq-module's PL IO-bank pins (4 LVDS - pairs, max. VCCIO - voltage: VIOTB)
9. 12-pin IDC header socket (vertical) J6 for access to Zynq-module's PL IO-bank pins (4 LVDS - pairs, max. VCCIO - voltage: VIOTB)
10. User Push-Button S2 ("RESTART" button by default)
11. User Push-Button S1 ("RESET" button by default)
12. User LEDs D6, D7, D8, D9 (function mapping depends on firmware of System - Controller - CPLD)
13. User LEDs D4, D5, D14, D15 (same as above)
14. Mini USB Connector (USB JTAG and UART Interface) J7
15. User 4-bit DIP-Switch S3
16. User 4-bit DIP-Switch S4
17. FTDI FT2232HQ USB 2.0 High Speed to UART/FIFO
18. Lattice Semiconductor MachXO2 1200HC System - Controller - CPLD
19. Jumper J4 to fix user button S2 to switched state
20. 40-Pin-Header J13 for access to PL IO-bank-pins
21. 40-Pin-Header J11 for access to PL IO-bank-pins
22. Samtec Razor Beam™ LSHM-150 B2B connector JB1
23. Samtec Razor Beam™ Beam™ LSHM-150 B2B connector JB2
24. Samtec Razor Beam™ Beam™ LSHM-130 B2B connector JB3
25. Barrel jack for 12V Power Supply power supply J10
26. Jumper J21 to select supply voltage VIOTB
27. Jumper J9, J19, J20 to select supply voltage USB-VBUS

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• Overvoltage-, undervoltage- and reversed- supply-voltage-protection
• Barrel jack for 12V power supply
• Carrier Board System - Controller - CPLD Lattice MachXO2 1200HC, programable by Mini-USB JTAG-Interface J7
• Zynq-module programable by ARM-JTAG-Interface-Connector (J15) or by System - Controller - CPLD via Mini-USB JTAG-Interface J7
• RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs
• 2x 40-Pin-Header J11 and J13  for access to Zynq-module's PL IO-bank-pins, operable with fixed (3.3V) or adjustable IO-voltage VIOTB (not usable as LVDS - pairs, only single-ended IOs)
  
• USB JTAG- and UART-Interface (FTDI FT2232HQ) with Mini-USB-Connector J7
  
• 8 x user LEDs routed to System - Controller - CPLD, 8 x red
• 2 x user-push button routed to System - Controller - CPLD; by default configured as system "RESET" and "RESTART" button (depends on CPLD-Firmware)
  
• 2 x 4-bit DIP-Switch for basebaseboard-board-configuration (3 switches routed to System - Controller - CPLD, 3 switches to set voltage FMC_VADJ, 1 switch routed to Zynq-module (MIO0), 1 switch enables Mini-USB JTAG-Interface J7)
  
• 12-pin IDC header socket (vertical) J5, J6 for access to Zynq-module's LVDS - pairs (max. VCCIO - voltage: VIOTB)
• 12-pin IDC header socket (right angle) J1 for access to Zynq-module's MIO0-bank-pins MIO0, MIO9 ... MIO15 (J1-6 (MIO12) buffered by Schmitt-Trigger-Buffer (5.0V Hysteresis), else max. VCCIO - voltage 3.3V)
• 12-pin IDC header socket (right angle) J2 for access to Zynq-module's PL IO-bank-pins (max. VCCIO - voltage: VIOTB)
  
• Micro SD card socket, can be used to boot system
• Micro-USB-Interface (J12) connected to Zynq-module (Device, Host or OTG modes)
• Trenz 4x5 4 x 5 module Socket (3 x Samtec LSHM series connectors)

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The TE0705 Carrier Board has on-board USB 2.0 High Speed to UART/FIFO IC FT2232HQ from FTDI. Channel A can be used as JTAG -Interface interface (MPSSE) to program the System - Controller - CPLD, Channel B can be used as UART -Interface interface routed to CPLD. There are also 6 additionally bus-lanes available for user-specific use. The FT2232HQ-Chip can also be used as FIFO in FT245 asynchronous mode.

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There are eight LEDs (D6, D7, D8, D9, D4, D5, D14, D15) available to the user. All LEDs are red colored and connected to the on-board System - Controller - CPLD. Their functions are programmable and depend on the firmware of the System - Controller - CPLD. For detailed information, please refer to the documentation of the TE0705 System - Controller - CPLD.

One green LED D22 shows the availability of the 3.3V supply voltage of the TE0705 Carrier Board.

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Table 1: Configuration of DIP-switch S3.

4-bit DIP-switch S4

Additionally, on the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (16) in Figure 1) available. The signals of the switch are routed to carrier board's System - Controller - CPLD and are fully user-configurable depending on a customer developed CPLD - firmware. Please refer to the documentation of the TE0705 System - Controller - CPLD to get information how to put these user-switches in operation.

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On the TE0705 Carrier Board there are two push buttons (S1 and S2) and are routed to the System - Controller - CPLD and available to the user. The default mapping of the push buttons is as follows:

Table 2: Description of the standard functionality of user push-buttons S1 and S2.

The functionality of the push buttons depends on the CPLD - firmware. For detailed information of the function of the push buttons, please refer to the documentation of the TE0705 System - Controller - CPLD.

Ethernet

The TE0701 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J14) with two LEDs.

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PHY LEDs are not connected directly to the module's B2B connectors as the 4x5 4 x 5 module have no dedicated PHY LED pins assigned. PHY LEDs are connected to the TE0705 System - Controller - CPLD, that can route those LEDs to some module's I/O Pins. In that case the CPLD has to map the PHY LEDs to corresponding pins.

See documentation of the TE0705 System - Controller - CPLD to get information of the function of the PHY LEDs.

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J5 and J6 sockets signal routing is done as differential pairs for pins 1-3, 2-4, 5-7, 6-8. The differential pairs are operable with VCCIO - voltage VIOTB.

Please use Master Pinout Table table as primary reference for the pin mapping information.

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Zynq-module's MIO0-bank pins MIO0, MIO9-MIO15 are accessible on socket J1. Maximal VCCIO - voltage is 3.3V on this socket. An exception here is the MIO12-pin, which is buffered with a Schmitt-Trigger-Buffer with a Hystersis of 5.0V.

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Zynq-module's PL IO-bank pins are accessible on socket J2. The IO-signals are routed from this socket to B2B-connector JB3 and are only single-ended IOs, hence this signal-pins are not usable as differential pairs. Maximal VCCIO - voltage is VIOTB on this socket.

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40-Pin-Header J11 and J13  for access to Zynq-module's PL IO-bank-pins on B2B-connectors JB1 and JB2. Operable with fixed (3.3V) or adjustable VCCIO - voltage VIOTB (not usable as LVDS - pairs, only single-ended IOs).

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Figure 3: Power-Up sequence diagram.

Configuring VCCIO 

On the TE0705 carrier board different VCCIO configurations can be chosen are selectable by jumper J21 and DIP-switch S3.

The purpose of the jumper and the DIP-switch S3 of the Carrier Board will be explained in the following sections.

Select VCCIO

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voltage by DIP-Switch S3

There is the possibility to select the module's PL IO-bank's supply voltage VIOTB to fixed adjustable voltages VADJ. Therefore, the jumper J21 has to be set to the position 1, 2-3, to connect the pins 'VIOTB' and 'ADJ'. On position 1-2, 3, the supply voltage VIOTB will be fixed to 3.3V

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Note: The configuration of VADJ depends on the used firmware of the System - Controller - CPLD. For detailed information, refer to the documentation of the TE0705 System - Controller - CPLD.

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The TE0705 carrier board can be configured as a USB host. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro USB port on J12). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the overcurrent over-current logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 100µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K (J9: 1-2, 3) or 10K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY on the mounted SoM, which is, in turn, connected to the Zynq FPGA. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (100 µF added).

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On the TE0705 carrier board all PL IO-bank's supply voltages of the 4x5 4 x 5 SoM (VCCIOA, VCCIOB, VCCIOC, VCCIOD; see 4x5 4 x 5 Module Integration Guide) are connected to the VCCIO - voltage VIOTB, which is either fixed to 3.3V (J21: 1-2, 3) or selectable with the adjustable supply-voltage VADJ (J21: 1, 2-3). The supply-voltages have following pin assignments on B2B-connectors:

base-board

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Table 4:

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baseboard supply-voltage VIOTB

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Following table describes how to configure the

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baseboard supply-voltages by jumpers:

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(J20: 1-2: additional decoupling-capacitor 100 µF)

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Table 5: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2, 3' means pins 1 and 2 are connected, 3 is open. 'Jx: 1, 2-3' means pins 2 and 3 are connected, 1 is open

Power On Reset (POR)

On the TE0705 the 5.0V and 3.3V power supply rails are generated by high performance DC-DC-converters from the external 12V supply. While the 3.3V plane supplies several on-board components (e.g., Lattice CPLD and FTDI Dual USB UART/FIFO IC), the 5V plane is mainly provided to power supply of the module to be carried (e.g., TE0720 Zynq SoC module). For the latter, however, special considerations must be taken (see TE0720 Power Supply). Therefore, the on-module system controller (SC) must be provided with information about the power-on-reset (POR) process, namely, the following control signals EN1, RESIN, and NOSEQ. And the SC provides, in turn, the status signal PGOOD down to the on-board System-Controller-CPLD.

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Table 5: Configuration of baseboard supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2, 3' means pins 1 and 2 are connected, 3 is open. 'Jx: 1, 2-3' means pins 2 and 3 are connected, 1 is open.

Table 6: Generation of PGOOD-signal

Technical Specifications

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