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Refer to https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TE0705 for downloadable version of this manual and additional technical documentation of the product.
The Trenz Electronic TE0705 carrier board provides functionality for testing, evaluation and development purposes of company's 4 x 5 cm SoMs (System on Module). Carrier board is equipped with broad range of various components and connectors for different configuration setups and needs. On-module functional components and multipurpose I/Os of the SoM's PL and PS logic are connected via board-to-board connectors to the carrier board components and connectors for easy user access.

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  1. ARM JTAG Connector (DS-5 D-Stream) J15 - PJTAG to EMIO multiplexing needed
  2. 12-pin IDC header socket J1 (right angle, max. VCCIO voltage 3.3V): mapped to 8 Zynq PS MIO0-bank-pins (MIO0, MIO9 to MIO15), 6 pins (MIO10 to MIO15) are additionally connected to TE0705 System Controller CPLD

  3. RJ45 GbE Connector

  4. SD Card Socket - Zynq SDIO0 Bootable SD port
  5. 12-pin IDC header socket (right angle) J2 for access to Zynq-module's PL IO-bank pins (not usable as LVDS pairs, only single-ended IOs, max. VCCIO voltage: VIOTB) J2
  6. Micro USB Connector J12 (Device, Host or OTG Micro USB Connector J12 (Device, Host or OTG Modes)
  7. Battery holder for CR1220 (RTC backup voltage)
  8. 12-pin IDC header socket (vertical) J5 for access to Zynq-module's PL IO-bank pins (4 LVDS pairs, max. VCCIO voltage: VIOTB)
  9. 12-pin IDC header socket (vertical) J6 for access to Zynq-module's PL IO-bank pins (4 LVDS pairs, max. VCCIO voltage: VIOTB) J6
  10. User Push-Button S2 ("User Push-Button S2 ("RESTART" button by default)
  11. User Push-Button S1 ("RESET" button by default)
  12. User LEDs D6, D7, D8, D9 (function mapping depends on firmware of System Controller CPLD)
  13. User LEDs D4, D5, D14, D15 (same as above)
  14. Mini USB Connector (USB JTAG and UART Interface) J7
  15. User 4-bit DIP-Switch S3
  16. User 4-bit DIP-Switch S4
  17. FTDI FT2232HQ USB 2.0 High Speed to UART/FIFO
  18. Lattice Semiconductor MachXO2 1200HC System Controller CPLD
  19. Jumper J4 to fix user button S2 to switched state
  20. 40-Pin-Header J13 for access to PL IO-bank-pins
  21. 40-Pin-Header J11 for access to PL IO-bank-pins
  22. Samtec Razor Beam™ LSHM-150 B2B connector JB1
  23. Samtec Razor Beam™ LSHM-150 B2B connector JB2
  24. Samtec Razor Beam™ LSHM-130 B2B connector JB3
  25. Barrel jack for 12V power supply J10
  26. Jumper J21 to select supply voltage VIOTB
  27. Jumper J9, J19, J20 to select supply voltage USB-VBUS

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  • Overvoltage-, undervoltage- and reversed- supply-voltage-protection
  • Barrel jack for 12V power supply
  • Carrier Board System Controller CPLD Lattice MachXO2 1200HC, programable by Mini-USB JTAG-Interface J7
  • Zynq-module SoM programable by ARM-JTAG-Interface-Connector (J15) or by System Controller CPLD via Mini-USB JTAG-Interface J7
  • RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs
  • 2x 40-Pin-Header J11 and J13  for access to Zynq- module's PL IO-bank-pins, operable with fixed (3.3V) or adjustable IO-voltage VIOTB (not usable as LVDS pairs, only single-ended IOs)

  • USB JTAG- and UART-Interface (FTDI FT2232HQ) with Mini-USB-USB JTAG- and UART-Interface (FTDI FT2232HQ) with Mini-USB-Connector J7
  • 8 x user LEDs routed to System Controller CPLD, 8 x red
  • 2 x user-push button routed to System Controller CPLD; by default (depending on CPLD-Firmware) configured as system "RESET" and "RESTART" button (depends on CPLD-Firmware)
  • 2 x 4-bit DIP-Switch for baseboard-configuration (3 switches routed to System Controller CPLD, 3 switches to set voltage FMC_VADJ, 1 switch routed to Zynq-module (MIO0), 1 switch enables Mini-USB JTAG-Interface J7)

  • 2 x 12-pin IDC header socket (vertical) J5, J6 for access to module's PL IO-bank-pins, usable as LVDS pairs
  • 2 x 12-pin IDC header socket (vertical) J5, J6 right angle) J1 and J2 for access to Zynq-module's LVDS pairs (max. VCCIO voltage: VIOTB)12-pin IDC header socket (right angle) J1 for access to Zynq-module's PL IO-bank-pins or MIO0-bank-pins MIO0, MIO9 ... MIO15 (J1-6 (MIO12) buffered by Schmitt-Trigger-Buffer (5.0V Hysteresis), else max. VCCIO voltage 3.3V)
  • 12-pin IDC header socket (right angle) J2 for access to Zynq-module's PL IO-bank-pins (max. VCCIO voltage: VIOTB)
  • Micro SD card socket, can be used to boot system
  • Micro-USB-Interface (J12) connected to Zynq-module (Device, Host or OTG modes)
  • Trenz 4 x 5 module Socket (3 x Samtec LSHM series connectors)

Interfaces and Pins

Micro SD Card Socket

  • if Zynq-module mounted
  • Micro SD card socket, can be used to boot system
  • Micro-USB-Interface (J12) connected to SoM's USB transceiver (Device, Host or OTG modes)
  • Trenz 4 x 5 module Socket (3 x Samtec LSHM series connectors)

Interfaces and Pins

Micro SD Card Socket

Micro SD Card socket is not directly wired to the B2B connector pins, but through a Texas Instruments TXS02612 SDIO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq-module. The Micro SD Card has 3.3V signal voltage level, but the MIO-bank on the Xilinx Zynq-module Micro SD Card socket is not directly wired to the B2B connector pins, but through a Texas Instruments TXS02612 SDIO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq-module. The Micro SD Card has 3.3V signal voltage level, but the MIO-bank on the Xilinx Zynq-module has VCCIO 1.8V.

Dual channel USB to UART/FIFO

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There are eight LEDs (D6, D7, D8, D9, D4, D5, D14, D15) available to the user. All LEDs are red colored and connected mapped to the on-board System Controller CPLD. Their functions are programmable and depend on the firmware of the System Controller CPLD. For detailed information, please refer to the documentation of the TE0705 System Controller CPLD.

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SwitchFunctionality
S3-1CM1: Mode pin 1 (routed to Carrier Controller)
S3-2CM0: Mode pin 0 (routed to Carrier Controller)
S3-3JTAGEN: Set to ON for normal JTAG operation. Must be moved to OFF position for TE0705 System Controller CPLD update only
S3-4 MIO0: Readable signal by System Controller CPLD and mounted TE07xx ModuleMIO0: Set MIO0-pin (on MIO0-Bank) on Zynq-modules, else low-active user IO-pin

Table 1: Configuration of DIP-switch S3.

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Additionally, on the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (16) in Figure 1) available. The signals of the switch are routed to carrier board's System Controller CPLD and are fully user-configurable depending on a customer developed CPLD firmware. Please refer to the documentation of the TE0705 System Controller CPLD to get information how to put these user-switches in operation.

The switches are connected to pull-up resistors and have a physical high-level of 3.3V on OFF-position.

User-Push-Buttons

On the TE0705 Carrier Board there are two push buttons (S1 and S2) and are routed to the System Controller CPLD and available to the user. The default mapping of the push buttons is as follows:

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The functionality of the push buttons depends on the CPLD firmware. For detailed information of the function of the push buttons, please refer to the documentation of the TE0705 System Controller CPLD.

Ethernet

The TE0701 TE0705 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J14) with two LEDs.

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PHY LEDs are not connected directly to the module's B2B connectors as the TE 4 x 5 module cm modules have no dedicated PHY LED pins assigned. PHY LEDs are connected to the TE0705 System Controller CPLD, that can route those LEDs to some the module's I/O IO Pins. In that case, the CPLD has to map the PHY LEDs to corresponding module's IO pins.

See documentation of the TE0705 System Controller CPLD to get information of the function of the PHY LEDs.

IDC header sockets J5 and J6

On the TE0705 there two IDC header available for access to Zynq-module's PL IO-bank pins

J5 and J6 sockets signal routing is done as differential pairs for pins 1-3, 2-4, 5-7, 6-8, hence 4 LVDS pairs are possible on this sockets. The differential pairs are operable with max. VCCIO voltage VIOTB.

Please use Master Pinout Table table as primary reference for the pin mapping information.

IDC header socket J1

IDC header socket J1

IDC header J1 provides access to SoM's PL IO-bank pins, whereby 6 pins (net name: 'MIO10' to 'MIO15') of this header are also routed to the System Controller CPLD.

If Zynq-module is mounted on the TE0705 carrier board, the pins of this header are routed to the corresponding pins of the PS logic of the SoM: Zynq-module's MIO0-bank pins MIO0, MIO9-MIO15 are accessible on socket header J1 and operable with max. Maximal VCCIO voltage is 3.3V on this socket.

An exception here is the 'MIO12'-pin, which is buffered with a Schmitt-Trigger-Buffer with a Hystersis of 5.0V.

IDC header socket J2

Zynq-moduleSoM's PL IO-bank pins are accessible on socket J2. The IO-signals are routed from this socket to B2B-connector JB3 and are only single-ended IOs, hence this signal-pins are not usable as differential pairs. Maximal VCCIO voltage is VIOTB on this socket.

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40-Pin-Header J11 and J13  for access to Zynq-module's PL IO-bank-pins on B2B-connectors JB1 and JB2. Operable with fixed (3.3V) or adjustable VCCIO voltage VIOTB (not usable as LVDS pairs, only single-ended IOs).

operable with fixed (3.3V) or adjustable IO-voltage VIOTB (not usable as LVDS pairs, only single-ended IOs).

Power

Power Supply

Power supply with minimum current capability of 3A at 12V for system startup is recommended.

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