Page History

...

HTML

<!--
Template Revision 1.4 beta
(HTML comment will not display, it's not needed to remove them. For Template/Skeleton changes, increase Template Revision number. So we can check faster, if the TRM style is up to date)
 -->

Scroll Ignore

Download PDF version of this document.

Scroll pdf ignore

Table of Contents

Table of Contents

Overview

Scroll Only (inline)
Refer to "https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803" for downloadable version of this manual and the rest of available documentation.

The Trenz Electronic TE0803 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+, max. 8 GByte DDR4 SDRAM with 64-Bit width data bus connection, max. 512 MByte SPI Boot Flash memory for configuration and operation, up to 8 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

All this in a compact 5.2 x 7.6 cm form factor, at the most competitive price.

...

Current TE0803 boards are equipped with ES1 silicon. Erratas and functional restrictions may exist, please check Xilinx documentation and contact your local Xilinx FAE for restrictions.

Key Features

Xilinx Zynq UltraScale+ MPSoC 784 pin package (options: ZU2CG, ZU2EG, ZU3CG, ZU3EG, ZU4CG, ZU4EV)
Memory
- 64-Bit DDR4, 8 GByte maximum
- Dual SPI boot Flash in parallel, 512 128 MByte maximum
User I/O
- 65 x MIO, 48 x HD (all), 156 x HP (3 banks)
- Serial transceiver: 4 x GTR (+ 4 x GTH transceiver with ZU4CG or ZU4EV MPSoC)
- Transceiver clocks inputs and outputs
- PLL clock generator inputs and outputs
Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
B2B connectors: 4 x 160 pin
Si5338A - 4 output PLL
All power supplies on board, single 3.3V power source required
- LP, FP, PL separately controlled power domains
Support for all boot modes (except NAND) and scenarios
Support for any combination of PS connected peripherals

...

Xilinx ZYNQ UltraScale+ MPSoC, U1
2-Input AND Gate, U39
Red LED (DONE), D1
256Mx16 DDR4-2400 SDRAM, U12
256Mx16 DDR4-2400 SDRAM, U9
256Mx16 DDR4-2400 SDRAM, U2
256Mx16 DDR4-2400 SDRAM, U3
12A PowerSoC DC-DC converter, U4 (either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)
1.5A LDO DC-DC converter, U10
1.5A LDO DC-DC converter, U8
Voltage monitor circuit, U41
0.35A LDO DC-DC converter, U26
0.35A LDO DC-DC converter, U27
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
4-channel programmable PLL clock generator, U5
Low-power programmable oscillator @ 25.000000 MHz, U5
Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
256 Mbit serial NOR Flash memory, U7
256 Mbit serial NOR Flash memory, U17

...

Storage device name	Content	Notes
User configuration EEPROMs with MAC address (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)	Not programmed	available since PCB REV02
SPI Flash main array	Not programmed	-
eFUSE Security	Not programmed	-
Si5338A programmable PLL NVM OTP	Not programmed-	Only volatile memory is programmable of field. NVM can't be program on field. Custom assembly variant with preprogrammed NVM is possible on request

Table 1: Initial Delivery State of the flash memories

...

Bank	Type	B2B Connector	Schematic Names / Connector Pins	I/O Signal Count	LVDS Pairs Count	VCCO Bank Voltage	Notes
25¹⁾	HD	J3	B25_L1_P ... B25_L12_P B25_L1_N ... B25_L12_N	24 I/O's	12	VCCO25 pins J3-15, J3-16	VCCO max. 3.3V usable as single-ended I/O's
26²⁾	HD	J3	B26_L1_P ... B26_L12_P B26_L1_N ... B26_L12_N	24 I/O's	12	VCCO26 pins J3-43, J3-44	VCCO max. 3.3V usable as single-ended I/O's
64	HP	J4	B64_L1_P ... B64_L24_P B64_L1_N ... B64_L24_N BB64_64_T0 ... BB64_64_T3	52 I/O's	24	VCCO64 pins J4-58, J4-106	VCCO max. 1.8V usable as single-ended I/O's
65	HP	J4	B65_L1_P ... B65_L24_P B65_L1_N ... B65_L24_N B_65B65_T0 ... BB65_65_T3	52 I/O's	24	VCCO65 pins J4-69, J4-105	VCCO max. 1.8V usable as single-ended I/O's
66	HP	J1	B66_L1_P ... B66_L24_P B66_L1_N ... B66_L24_N B_65B66_T0 ... BB66_65_T3	52 I/O's	24	VCCO66 pins J1-90, J1-120	VCCO max. 1.8V usable as single-ended I/O's
500	MIO	J3	MIO13 ... MIO25	13 I/O's	-	PS_1V8	user configurable I/O's on B2B
501	MIO	J3	MIO26 ... MIO51	26 I/O's	-	PS_1V8	user configurable I/O's on B2B
502	MIO	J3	MIO52 ... MIO77	26 I/O's	-	PS_1V8	user configurable I/O's on B2B

...

Bank

Type

B2B Connector

Count of MGT Lanes

Schematic Names / Connector Pins

MGT Bank's Reference Clock Inputs

224¹⁾

GTH

J1

4 GTH lanes

(4 RX / 4TX)

B224_RX3_P, B224_RX3_N, pins J1-51, J1-53
B224_TX3_P, B224_TX3_N, pins J1-50, J1-52

B224_RX2_P, B224_RX2_N, pins J1-57, J1-59
B224_TX2_P, B224_TX2_N, pins J1-56, J1-58

B224_RX1_P, B224_RX1_N, pins J1-63, J1-65
B224_TX1_P, B224_TX1_N, pins J1-62, J1-64

B224_RX0_P, B224_RX0_N, pins J1-69, J1-71
B224_TX0_P, B224_TX0_N, pins J1-68, J1-70

1 reference clock signal (B224_CLK0) from B2B connector
J3 (pins J3-59/J3-61) to bank's pins Y6/Y5

1 reference clock signal (B224_CLK1) from programmable
PLL clock generator U5 to bank's pins V6/V5

505

GTR

J2

4 GTR lanes

(4 RX / 4TX)

B505_RX3_P, B505_RX3_N, pins J2-5154, J2-4952
B505_TX3_P, B505_TX3_N, pins J2-5451, J2-5249

B505_RX2_P, B505_RX2_N, pins J2-5760, J2-5558
B505_TX2_P, B505_TX2_N, pins J2-6057, J2-5855

B505_RX1_P, B505_RX1_N, pins J2-6366, J2-6164
B505_TX1_P, B505_TX1_N, pins J2-6663, J2-6461

B505_RX0_P, B505_RX0_N, pins J2-6972, J2-6770
B505_TX0_P, B505_TX0_N, pins J2-7269, J2-7067

2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector
J2 (pins J2-16/J2-18, J2-10/J2-12) to bank's pins F23/F24, E21/E22

2 reference clock signals (B505_CLK2, B505_CLK3) from programmable
PLL clock generator U5 to bank's pins C21/C22, A21/A22

...

1) Bank 224 only available at ZU4CG or ZU4EV at XCZU4 / XCZU5 MPSoC.

Page break

JTAG Interface

...

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO0..MIO5 and MIO7..MIO12.

MIO	U7 Pin	Pin Name	MIO	U17 Pin	Pin Name
0	B2	CLK	7	C2	CS#
1	D2	DO/IO1	8	D3	DI/IO0
2	C4	WP#/IO2	9	D2	DO/IO1
3	D4	HOLD#/IO3	10	C4	WP#/IO2
4	D3	DI/IO0	11	D4	HOLD#/IO3
5	C2	CS#	12	B2	CLK

Table 7: MIO pin assignment of the Quad SPI Flash memory ICs

...

The TE0803 SoM can be configured with max. 512 MByte Flash memory for configuration and operation. Flash size and type depends on assembly version.

NameIC	Designator	PS7	MIO	Notes
SPI FlashN25Q256A11E1240E	U7	QSPI0	MIO0 ... MIO5	Dual parallel booting possible, 32 MByte memory per Flash IC at standard configuration
SPI Flash	N25Q256A11E1240E	U17	QSPI0	MIO7 ... MIO12	As above

...

The TE0803-01 SoM is equipped with with four DDR4-2400 SDRAM modules chips with up to 8 GByte of memory. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) via 64-bit wide data bus.

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information, if the specific Zynq UltraScale+ MPSoC chip on module supports the maximum data transmission rate of 2400 MByte/s.

Programmable PLL Clock Generator

Configuration EEPROM

The TE0803 (PCB REV02 or newer) contains EEPROMs for general user purposes and mac address. The EEPROMs are provided by Microchip and all have I²C interfaces:

EEPROM Modell	Schematic Designator	Memory Density	Purpose
24AA025E48T-I/OT	U41	2 Kbit	user

Table 21: On-board configuration EEPROMs overview

Programmable PLL Clock Generator

Following table illustrates on-board Si5338A programmable clock multiplier chip inputs and Following table illustrates on-board Si5338A programmable clock multiplier chip inputs and outputs:

Input	Connected to	Frequency	Notes
IN1 / IN2	B2B Connector pins J2-4, J2-6 (differential pair)	User	AC decoupling required on base
IN3	On-board Oscillator (U6)	25.000000 MHz	-
Output	Connected to	Frequency	Notes
CLK0 A/B	B2B Connector pins J2-1, J2-3 (differential pair)	User	Default off
CLK1 A/B	B224 CLK1 (only available at ZU5EV MPSoC with ZU4 and higher )	User	Default off
CLK2 A/B	B505 CLK3	User	Default off
CLK3 A/B	B505 CLK2	User	Default off

Table 11: Programmable PLL clock generator input/output

The Si5345A Si5338A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5338A data sheet.

...

Table 12: B2B connector pin-out of Si5338A control interface

Note
Si5338A OTP ROM Si5338A NVM is not programmed by default at delivery, so it . It is customers responsibility to either configure Si5338A volatile memory during FSBL or then use Silicon Labs programmer and burn the OTP ROM with customer fixed clock setup.

...

. Custom assembly variant with preprogrammed NVM is possible on request.

Refer to Si5338A datasheet for more information.

...

Figure 3: Power Distribution Diagram (For U4 either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)

Note
Current rating of Samtec Razor Beam™ LSHMBeam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 21.0A 5 A per pin (2 adjacent pins powered1 pin powered per row).

Power-On Sequence Diagram

...

Enable-Signal	B2B Connector Pin	Max. Voltage	Note	Power-Good-Signal	B2B Connector Pin	Pull-up Resistor	Note
EN_LPD	J2-108	6V	TPS82085SIL data sheet	LP_GOOD	J2-106	4K7, pulled up to LP_DCDC	-
EN_FPD	J2-102	DCDCIN	NC7S08P5X data sheet	PG_FPD	J2-110	4K7, pulled up to DCDCIN	-
EN_PL	J2-101	max PL_DCIN	Left floating for logic high (drive to GND for logic low)	PG_PL	J2-104	External pull-up needed (max. voltage 'GT_DCDC'), Max. sink current 1 mA	TPS82085SIL / NC7S08P5X datasheet
EN_DDR	J2-112	DCDCIN	NC7S08P5X data sheet	PG_DDR	J2-114	4K7, pulled up to DCDCIN	-
EN_PSGT	J2-84	DCDCIN	NC7S08P5X data sheet	PG_PSGT	J2-82	External pull-up needed (max. 5.5V), Max. sink current 1 mA	TPS74801 datasheet
EN_GT_R	J2-95	GT_DCDC	NC7S08P5X data sheet	PG_GT_R	J2-91	External pull-up needed (max. 5.5V), Max. sink current 1 mA	TPS74401 datasheet
-	-	-	-	PG_VCU_1V0	J2-97	External pull-up needed (max. 5.5V), Max. sink current 1 mA	TPS82085SIL datasheet

Table 16: Recommended operation conditions of DC-DC converter control signals

Warning
To avoid any damage to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/O's should be tri-stated during power-on sequence.

...

Voltages on B2B Connectors	B2B J1 Pin	B2B J2 Pin	B2B J3 Pin	B2B J4 Pin	Input/ Output	Note
PL_DCIN	J1-151, J1-153,J1-155, J1-157, J1-159	-	-	-	Input	-
DCDCIN	-	J2-154, J2-156, J2-158, J2-160, J2-153, J2-155, J2-157, J2-159	-	-	Input	-
LP_DCDC	-	J2-138, J2-140, J2-142, J2-144	-	-	Input	-
PS_BATT	-	J2-125	-	-	Input	-
GT_DCDC	-	-	J3-157, J3-158, J3-159, J3-160	-	Input	-
PS_1V8	-	J2-99	J3-147, J3-148	-	Output	Internal voltage level 1.8V nominal output
PL_1V8	J1-91, J1-121	-	-	-	Output	Internal voltage level 1.8V nominal output
DDR_1V2	-	J2-135	-	-	Output	Internal voltage level 1.2V nominal output

...

B2B connectors

Include Page

	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors
	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors	IN:SS5-ST5 connectors	IN:SS5-ST5 connectors

Variants Currently In Production

...

Trenz shop TE0803 overview page
English page	German page

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	-0.3	4	V	TPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG
DCDCIN	-0.3	4	V	TPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC	-0.3	4	V	TPS3106K33DBVR data sheet
GT_DCDC	-0.3	4	V	TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
PS_BATT	-0.5	2	V	Xilinx DS925 data sheet
VCCO for HD I/O banks	-0.5	3.4	V	Xilinx DS925 data sheet
VCCO for HP I/O banks	-0.5	2	V	Xilinx DS925 data sheet
VREF	-0.5	2	V	Xilinx DS925 data sheet
I/O input voltage for HD I/O banks	-0.55	VCCO + 0.55	V	Xilinx DS925 data sheet
I/O input voltage for HP

Table 19: Differences between module TE0803-01 variants

1) Not yet available

All variants are rated for Extended operating temperature range (0 - 100 °C).

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	-0.3	7	V	TPS82085SIL / EN63A0QI data sheet
DCDCIN	-0.3	7	V	TPS82085SIL / TPS51206PSQ data sheet
LP_DCDC	-0.3	4	V	TPS3106K33DBVR data sheet
GT_DCDC	-0.3	7	V	TPS82085SIL data sheet
PS_BATT	-0.5	2	V	Xilinx DS925 data sheet
VCCO for HD I/O banks	-0.555	3VCCO + 0.455	V	Xilinx DS925 data sheet
VCCO for HP PS I/O banksinput voltage (MIO pins)	-0.52	VCCO_PSIO + 0.55	V	Xilinx DS925 data sheet
VREF	-0.5	2	V	Xilinx DS925 data sheet
, VCCO_PSIO 1.8V nominally
Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltageI/O input voltage for HD I/O banks	-0.555VCCO + 0	1.552	V	Xilinx DS925 data sheet
I/O input voltage for HP I/O banksVoltage on input pins of NC7S08P5X 2-Input AND Gate	-0.555	VCCO VCC + 0.555	V	Xilinx DS925 NC7S08P5X data sheet, see schematic for VCC
Voltage on input pins (nMR) of TPS3106K33DBVR Voltage Monitor, U41PS I/O input voltage (MIO pins)	-0.53	VCCO_PSIO VDD + 0.553	V	Xilinx DS925 TPS3106 data sheet, VCCO_PSIO 1.8V nominallyVDD = LP_DCDC
"Enable"-signals on TPS82085SIL ('EN_LPD')Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage	-0.531.	27	V	Xilinx DS925 TPS82085SIL data sheet
Voltage on input pins of NC7S08P5X 2-Input AND Gate	-0.5	VCC + 0.5	V	NC7S08P5X data sheet, see schematic for VCC
Voltage on input pins (nMR) of TPS3106K33DBVR Voltage Monitor, U41	-0.3	VDD + 0.3	V	TPS3106 data sheet, VDD = LP_DCDC
"Enable"-signals on TPS82085SIL ('EN_LPD')	-0.3	7	V	TPS82085SIL data sheet
Storage temperature (ambient)	-40	100	°C	ROHM Semiconductor SML-P11 Series data sheet

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

Storage temperature (ambient)

-40

100

°C

ROHM Semiconductor SML-P11 Series data sheet

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	3.3	3.6	V	EN63A0QI / TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
DCDCIN	3.3	3.6	V	TPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC	3.3	3.6	V	TPS3106K33DBVR data sheet
GT_DCDC	3.3	3.6	V	TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	2.5	6	V	EN63A0QI / TPS82085SIL data sheet
DCDCIN	3.1	6	V	TPS82085SIL / TPS51206PSQ data sheet
LP_DCDC	2.5	3.6	V	TPS82085SIL / TPS3106K33DBVR data sheet
GT_DCDC	2.5	6	V	TPS82085SIL data sheet
PS_BATT	1.2	1.5	V	Xilinx DS925 data sheet
VCCO for HD I/O banks	1.14	3.4	V	Xilinx DS925 data sheet
VCCO for HP I/O banks	0.95	1.9	V	Xilinx DS925 data sheet
I/O input voltage for HD I/O banks.	-0.2	VCCO + 0.2	V	Xilinx DS925 data sheet
I/O input voltage for HP I/O banks	-0.2	VCCO + 0.2	V	Xilinx DS925 data sheet
PS I/O input voltage (MIO pins)	-0.2	VCCO_PSIO + 0.2	V	Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally
Voltage on input pins of NC7S08P5X 2-Input AND Gate	0	VCC	V	NC7S08P5X data sheet, see schematic for connected VCCs
Voltage on input pins (MR) of TPS3106K33DBVR Voltage Monitor, U41	0	VDD	V	TPS3106 data sheet, VDD = LP_DCDC

...

Operating Temperature Ranges

Extended grade: 0°C to +100°C.

The module operating temperature The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

...

Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm5mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

...

Date	Revision	Notes	Link to PCN	Documentation Link
2016-12-23	01	First production release	-	TE0803-01

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Image Removed

Document Change History


2019-03-18	03	Added support of DDP DDR4 Added support of Low power FPGA (-L1/L2). Revised testpoints Revised J1-J4 connectors net label style	TE0803 Product Change Notifications	TE0803-03
2018-07-19	02	Added LDO to DDR_PLL All differential pairs length matched with tollerance 0.1mm (excluding package delays) Added MAC EEPROM U28 VPS_MGTRAVCC set to 0.85V Added pull-up resistors R68, R69	TE0803 Product Change Notifications	TE0803-02
2016-12-23	01	First production release	-	TE0803-01

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Image Added

Document Change History

Date

Revision

Contributors

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

Page info

infoType	Modified by
type	Flat

Added note regarding DCDC U4.

22-02-25

v.50

John Hartfiel

Add Note to PLL

22-02-08

v.46

John Hartfiel

Correction on Power section
Correction GTH Clock connection

2021-05-17

v.41

John Hartfiel

typo correction in DDR section

2021-03-11

v.40

John Hartfiel

typo
fixed MGT Lanes RX/TX order

2019-07-15

v.36

John Hartfiel

correction SPLL section

2019-07-02

v.35

John Hartfiel

add eeprom section
update PCB Revision section

2019-06-19

v.33

John Hartfiel

update links
correction flash section

2018-08-20

v.29

John Hartfiel

power section: add missing PS_1V8 output pin

2018-08-06

v.28

John Hartfiel

typo correction

2017-11-13

v.23

Ali Naseri

updated B2B connector max. current rating per pin

2017-11-13

v.19

John Hartfiel

rework B2B section

2017-10-19

v.18

John Hartfiel

Removed ES1 Note

2017-08-15

v.17

Vitali Tsiukala

Changed Signals Count in the table B2B-connectors

2017-08-07

v.14

Date

Revision

Contributors

Description

2017-08-07

Jan Kumann

New smaller images.
New QSPI Flash MIO mapping table.
Temperature information changes.
Few corrections.

2017-05-17

V.4

Ali Naseri

Current TRM release.

2017-05-10

v.1

Ali Naseri

Initial document.

...

Trenz Electronic Documentation

Versions Compared

Old Version 15

New Version Current

Key

Overview

Key Features

JTAG Interface

Programmable PLL Clock Generator

Configuration EEPROM

Programmable PLL Clock Generator

Power-On Sequence Diagram

B2B connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Recommended Operating Conditions

Operating Temperature Ranges

Document Change History

Document Change History