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MGT Lanes

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  1. Xilinx ZYNQ UltraScale+ MPSoC, U1
  2. 2-Input AND Gate, U39
  3. Red LED (DONE), D1
  4. 256Mx16 DDR4-2400 SDRAM, U12
  5. 256Mx16 DDR4-2400 SDRAM, U9
  6. 256Mx16 DDR4-2400 SDRAM, U2
  7. 256Mx16 DDR4-2400 SDRAM, U3
  8. 12A PowerSoC DC-DC converter, U4 (either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)
  9. 1.5A LDO DC-DC converter, U10
  10. 1.5A LDO DC-DC converter, U8
  11. Voltage monitor circuit, U41
  12. 0.35A LDO DC-DC converter, U26
  13. 0.35A LDO DC-DC converter, U27
  14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  18. 4-channel programmable PLL clock generator, U5
  19. Low-power programmable oscillator @ 25.000000 MHz, U5
  20. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
  21. 256 Mbit serial NOR Flash memory, U7
  22. 256 Mbit serial NOR Flash memory, U17

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 Storage device name

Content

Notes

User configuration EEPROMs with MAC address (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)

Not programmed

available since PCB REV02

SPI Flash main array

Not programmed

-

eFUSE Security

Not programmed

-
Si5338A programmable PLL NVM OTPNot programmed-Only volatile memory is programmable of field. NVM can't be program on field. Custom assembly variant with preprogrammed NVM is possible on request

Table 1: Initial Delivery State of the flash memories

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The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.

Page break

MGT Lanes

The B2B connectors J1 and J2 provide also access to the MGT banks of the Zynq UltraScale+ MPSoC. There are 8 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).

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InputConnected toFrequencyNotes
IN1 / IN2B2B Connector pins J2-4, J2-6 (differential pair)UserAC decoupling required on base
IN3On-board Oscillator (U6)25.000000 MHz-
OutputConnected toFrequencyNotes
CLK0 A/BB2B Connector pins J2-1, J2-3 (differential pair)UserDefault off
CLK1 A/BB224 CLK1 (only available at ZU5EV MPSoC with ZU4 and higher )UserDefault off
CLK2 A/BB505 CLK3UserDefault off
CLK3 A/BB505 CLK2UserDefault off

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Table 12: B2B connector pin-out of Si5338A control interface

Note

Si5338A OTP ROM Si5338A  NVM  is not programmed by default at delivery, so it . It is customers responsibility to either configure Si5338A volatile memory during FSBL or then use Silicon Labs programmer.  Custom assembly variant with preprogrammed NVM is possible on request.

Refer to Si5338A datasheet for more information.

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Figure 3: Power Distribution Diagram (For U4 either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)

Note

Current

Note

Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row).

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Voltages on B2B
Connectors		B2B J1 PinB2B J2 PinB2B J3 PinB2B J4 PinInput/
Output		Note
PL_DCINJ1-151, J1-153,J1-155, J1-157, J1-159---Input-
DCDCIN-J2-154, J2-156, J2-158, J2-160,
J2-153, J2-155, J2-157, J2-159		--Input-
LP_DCDC-J2-138, J2-140, J2-142, J2-144--Input-
PS_BATT-J2-125--Input-
GT_DCDC--J3-157, J3-158, J3-159, J3-160-Input-
PS_1V8-J2-99J3-147, J3-148-OutputInternal voltage level
1.8V nominal output
PL_1V8J1-91, J1-121---OutputInternal voltage level
1.8V nominal output
DDR_1V2-J2-135--OutputInternal voltage level
1.2V nominal output

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ParameterMinMaxUnitNotes / Reference Document
PL_DCIN-0.374VTPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG
DCDCIN-0.374VTPS82085SIL  TPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.374VTPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
PS_BATT-0.52VXilinx DS925 data sheet
VCCO for HD I/O banks-0.53.4VXilinx DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx DS925 data sheet
VREF-0.52VXilinx DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage		-0.51.2VXilinx DS925 data sheet
Voltage on input pins of
NC7S08P5X 2-Input AND Gate		-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC
Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41		-0.3VDD + 0.3VTPS3106 data sheet,
VDD = LP_DCDC
"Enable"-signals on TPS82085SIL
('EN_LPD')		-0.37VTPS82085SIL data sheet
Storage temperature (ambient)-40100°CROHM Semiconductor SML-P11 Series data sheet

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ParameterMinMaxUnitNotes / Reference Document
PL_DCIN23.533.6VEN63A0QI / TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
DCDCIN3.133.6VTPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC23.533.6VTPS82085SIL / TPS3106K33DBVR data sheet
GT_DCDC23.533.6VTPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
PS_BATT1.21.5VXilinx DS925 data sheet
VCCO for HD I/O banks1.143.4VXilinx DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Voltage on input pins of
NC7S08P5X 2-Input AND Gate		0VCCVNC7S08P5X data sheet,
see schematic for connected VCCs
Voltage on input pins (MR) of
TPS3106K33DBVR Voltage Monitor, U41		0VDDVTPS3106 data sheet,
VDD = LP_DCDC

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  • Added note regarding DCDC U4.
22-02-25


v.50


John Hartfiel


  • Add Note to PLL
22-02-08v.46John Hartfiel
  • Correction on Power section
  • Correction GTH Clock connection
2021-05-17v.41John Hartfiel
  • typo correction in DDR section
2021-03-11v.40John Hartfiel
  • typo
  • fixed MGT Lanes RX/TX order
2019-07-15v.36John Hartfiel
  • correction SPLL section
2019-07-02v.35John Hartfiel
  • add eeprom section
  • update PCB Revision section
2019-06-19v.33John Hartfiel
  • update links
  • correction flash section

2018-08-20

v.29John Hartfiel
  • power section: add missing PS_1V8 output pin

2018-08-06

v.28John Hartfiel
  • typo correction
2017-11-13v.23Ali Naseri
  • updated B2B connector max. current rating per pin

2017-11-13

v.19



John Hartfiel
  • rework B2B section
2017-10-19

v.18

John Hartfiel
  • Removed ES1 Note
2017-08-15v.17Vitali Tsiukala
  • Changed Signals Count in the table B2B-connectors

2017-08-07


v.14

Jan Kumann
  • New smaller images.
  • New QSPI Flash MIO mapping table.
  • Temperature information changes.
  • Few corrections.

2017-05-17

V.4


Ali NaseriCurrent TRM release.
2017-05-10v.1Ali NaseriInitial document.

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